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ADC08D1500EVAL Datasheet

  • ADC08D1500EVAL

  • High Performance, Low Power, Dual 8-Bit, 1.5 GSPS A/D Conver...

  • 861.71KB

  • 33页

  • NSC

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ADC08D1500
1.0 Functional Description
I-Channel Offset
Addr: 2h (0010b)
D15
(MSB)
D7
Sign
Bits 15:8
D6
1
D5
1
D14
D13
D12
D11
(Continued)
Q-Channel Offset
Addr: Ah (1010b)
W only (0x007F)
D12
D11
D10
D9
D8
(LSB)
D2
1
D1
1
D0
1
W only (0x007F)
D10
D9
D8
(LSB)
D2
1
D1
1
D0
1
D15
(MSB)
D7
Sign
Bit 15:8
D14
D13
Offset Value
D6
1
D5
1
D4
1
D3
1
Offset Value
D4
1
D3
1
Offset Value. The input offset of the
I-Channel ADC is adjusted linearly and
monotonically by the value in this field. 00h
provides a nominal zero offset, while FFh
provides a nominal 45 mV of offset. Thus,
each code step provides 0.176 mV of offset.
POR State: 0000 0000 b
Bit 7
Sign bit. 0b gives positive offset, 1b gives
negative offset.
POR State: 0b
Bit 6:0
Must be set to 1b
Offset Value. The input offset of the
Q-Channel ADC is adjusted linearly and
monotonically by the value in this field. 00h
provides a nominal zero offset, while FFh
provides a nominal 45 mV of offset. Thus,
each code step provides about 0.176 mV of
offset.
POR State: 0000 0000 b
Sign bit. 0b gives positive offset, 1b gives
negative offset.
POR State: 0b
Must be set to 1b
Q-Channel Full-Scale Voltage Adjust
Bit 7
Bit 6:0
I-Channel Full-Scale Voltage Adjust
Addr: 3h (0011b)
W only (0x807F)
Addr: Bh (1011b)
D15
(MSB)
D14
D13
D12
D11
W only (0x807F)
D10
D9
D8
Adjust Value
D6
1
D5
1
D4
1
D3
1
D2
1
D1
1
D0
1
D15
(MSB)
D7
(LSB)
Bit 15:7
D14
D13
D12
D11
D10
D9
D8
D7
(LSB)
Adjust Value
D6
1
D5
1
D4
1
D3
1
D2
1
D1
1
D0
1
Bit 15:7
Full Scale Voltage Adjust Value. The input
full-scale voltage or gain of the I-Channel
ADC is adjusted linearly and monotonically
with a 9 bit data value. The adjustment range
is
卤
20% of the nominal 700 mV
P-P
differential value.
0000 0000 0
1000 0000 0
Default Value
1111 1111 1
560mV
P-P
700mV
P-P
840mV
P-P
Full Scale Voltage Adjust Value. The input
full-scale voltage or gain of the I-Channel
ADC is adjusted linearly and monotonically
with a 9 bit data value. The adjustment
range is
卤
20% of the nominal 700 mV
P-P
differential value.
0000 0000 0
1000 0000 0
1111 1111 1
560mV
P-P
700mV
P-P
840mV
P-P
For best performance, it is recommended
that the value in this field be limited to the
range of 0110 0000 0b to 1110 0000 0b. i.e.,
limit the amount of adjustment to
卤
15%. The
remaining
卤
5% headroom allows for the
ADC鈥檚 own full scale variation. A gain
adjustment
does
not
require
ADC
re-calibration.
POR State: 1000 0000 0b (no adjustment)
Bits 6:0
Must be set to 1b
For best performance, it is recommended
that the value in this field be limited to the
range of 0110 0000 0b to 1110 0000 0b.
i.e., limit the amount of adjustment to
卤
15%.
The remaining
卤
5% headroom allows for
the ADC鈥檚 own full scale variation. A gain
adjustment does not require ADC
re-calibration.
POR State: 1000 0000 0b (no adjustment)
Bits 6:0
Must be set to 1b
23
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