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PSD813F2 Datasheet

  • PSD813F2

  • FLASH IN-SYSTEM PROGRAMMABLE (ISP) PERIPHERALS FOR 8-BIT MCU...

  • 1180.57KB

  • STMicroelectronics   STMicroelectronics

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PSD8XX Family
PSD835G2
Pin*
(TQFP
Pin Name Pkg.)
PE3
74
Table 5.
PSD835G2
Pin
Descriptions
(cont.)
Type
I/O
CMOS
or Open
Drain
I/O
CMOS
or Open
Drain
Description
Port E, PE3. This port is pin configurable and has multiple
functions:
1. MCU I/O 鈥?standard output or input port.
2. Latched address output.
3. TDO output for JTAG/ISP interface.
Port E, PE4. This port is pin configurable and has multiple
functions:
1. MCU I/O 鈥?standard output or input port.
2. Latched address output.
3. TSTAT output for the ISP interface.
4. Rdy/Bsy 鈥?for in-circuit Parallel Programming.
Port E, PE5. This port is pin configurable and has multiple
functions:
1. MCU I/O 鈥?standard output or input port.
2. Latched address output.
3. TERR active low output for ISP interface.
Port E, PE6. This port is pin configurable and has multiple
functions:
1. MCU I/O 鈥?standard output or input port.
2. Latched address output.
3. Vstby 鈥?SRAM standby voltage input for battery
backup SRAM
Port E, PE7. This port is pin configurable and has multiple
functions:
1. MCU I/O 鈥?standard output or input port.
2. Latched address output.
3. Vbaton 鈥?battery backup indicator output. Goes high when
power is drawn from an external battery.
Port F, PF0-7. This port is pin configurable and has multiple
functions:
1. MCU I/O 鈥?standard output or input port.
2. Input to the PLD.
3. Latched address outputs.
4. As address A0-3 inputs in 80C51XA mode
5. As data bus port (D0-7) in non-multiplexed bus configuration
Port G, PG0-7. This port is pin configurable and has multiple
functions:
1. MCU I/O 鈥?standard output or input port.
2. Latched address outputs.
PE4
75
PE5
76
I/O
CMOS
or Open
Drain
I/O
CMOS
or Open
Drain
PE6
77
PE7
78
I/O
CMOS
or Open
Drain
PF0-PF7
31-38
I/O
CMOS
or Open
Drain
PG0-PG7 21-28
I/O
CMOS
or Open
Drain
GND
8,30,
49,50,
70
9,29,
69
V
CC
10

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