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PSD813F2数据手册封面

PSD813F2 Datasheet

  • PSD813F2

  • FLASH IN-SYSTEM PROGRAMMABLE (ISP) PERIPHERALS FOR 8-BIT MCU...

  • 1180.57KB

  • STMicroelectronics   STMicroelectronics

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PSD835G2
PSD8XX Family
The
PSD835G2
Functional
Blocks
(cont.)
9.5.3 Reset and Power On Requirement
9.5.3.1 Power On Reset
Upon power up the PSD835G2 requires a reset pulse of tNLNH-PO (minimum 1 ms) after
V
CC
is steady. During this time period the device loads internal configurations, clears
some of the registers and sets the Flash into operating mode. After the rising edge of
reset, the PSD835G2 remains in the reset state for an additional tOPR (maximum 120 ns)
nanoseconds before the first memory access is allowed.
The PSD835G2 Flash memory is reset to the read array mode upon power up. The FSi
and CSBOOTi select signals along with the write strobe signal must be in the false
state during power-up reset for maximum security of the data contents and to remove
the possibility of data being written on the first edge of a write strobe signal. Any Flash
memory write cycle initiation is prevented automatically when V
CC
is below VLKO.
9.5.3.2 Warm Reset
Once the device is up and running, the device can be reset with a much shorter pulse of
tNLNH (minimum 150 ns). The same tOPR time is needed before the device is operational
after warm reset. Figure 31 shows the timing of the power on and warm reset.
Figure 31. Power On and Warm Reset Timing
OPERATING LEVEL
t NLNH鈥?PO
V
CC
t NLNH
t NLNH-A
RESET
t OPR
POWER ON RESET
WARM
RESET
t OPR
9.5.3.3
I/O Pin, Register and PLD Status at Reset
Table 29 shows the I/O pin, register and PLD status during power on reset, warm reset
and power down mode. PLD outputs are always valid during warm reset, and they are
valid in power on reset once the internal PSD configuration bits are loaded. This loading of
PSD is completed typically long before the V
CC
ramps up to operating level. Once the PLD
is active, the state of the outputs are determined by the equations specified in PSDsoft.
69

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