PSD835G2
PSD8XX Family
Table 6 shows the offset addresses to the PSD835G2 registers relative to the CSIOP base
address. The CSIOP space is the 256 bytes of address that is allocated by the user to the
internal PSD835G2 registers. Table 6 provides brief descriptions of the registers in CSIOP
space. For a more detailed description, refer to section 9.
7.0 PSD835G2
Register
Description and
Address Offset
Table 6. Register Address Offset
Register Name
Data In
Control
Data Out
Direction
04
06
05
07
14
16
15
17
Port A
00
Port B
01
Port C
10
Port D
11
Port E
30
32
34
36
Port F
40
42
44
46
Port G
41
43
45
47
Other*
Description
Reads Port pin as input,
MCU I/O input mode
Selects mode between
MCU I/O or Address Out
Stores data for output
to Port pins, MCU I/O
output mode
Configures Port pin as
input or output
Configures Port pins as
either CMOS or Open
Drain on some pins, while
selecting high slew rate
on other pins.
Reads Input Micro鈬擟ells
Reads the status of the
output enable to the I/O
Port driver
Read 鈥?reads output of
Micro鈬擟ells A
Write 鈥?loads Micro鈬攃ell
Flip-Flops
Read 鈥?reads output of
Micro鈬擟ells B
Write 鈥?loads Micro鈬攃ell
Flip-Flops
Blocks writing to the
Output Micro鈬擟ells A
Blocks writing to the
Output Micro鈬擟ells B
Read only 鈥?Flash Sector
Protection
Read only 鈥?PSD Security
and Flash Boot Sector
Protection
Enables JTAG Port
Power Management
Register 0
Power Management
Register 2
Page Register
Places PSD memory
areas in Program and/or
Data space on an
individual basis.
Read only 鈥?Flash and
SRAM size
Read only 鈥?Boot type
and size
Drive Select
08
09
18
19
38
48
49
Input Micro鈬擟ell
Enable Out
0A
0C
0B
0D
1C
1A
4C
Output
Micro鈬擟ells A
20
Output
Micro鈬擟ells B
Mask
Micro鈬擟ells A
Mask
Micro鈬擟ells B
Flash Protection
Flash Boot
Protection
JTAG Enable
PMMR0
PMMR2
Page
VM
22
21
23
C0
C2
C7
B0
B4
E0
E2
Memory_ID0
Memory_ID1
F0
F1
11