PSD835G2
PSD8XX Family
The
PSD835G2
Functional
Blocks
(cont.)
Figure 6. Priority Level of Memory and I/O Components
Highest Priority
Level 1
SRAM, I/O, or
Peripheral I/O
Level 2
Secondary Flash Memory
Level 3
Main Flash Memory
Lowest Priority
9.1.3.1. Memory Select Configuration for MCUs with Separate Program and Data Spaces
The 80C51 and compatible family of microcontrollers, can be configured to have separate
address spaces for code memory (selected using PSEN) and data memory (selected using
RD). Any of the memories within the PSD835G2 can reside in either space or both spaces.
This is controlled through manipulation of the VM register that resides in the PSD鈥檚 CSIOP
space.
The VM register is set using PSDsoft to have an initial value. It can subsequently be
changed by the microcontroller so that memory mapping can be changed on-the-fly.
For example, you may wish to have SRAM and main Flash in Data Space at boot, and
secondary Flash memory in Program Space at boot, and later swap main and secondary
Flash memory. This is easily done with the VM register by using PSDsoft to configure it for
boot up and having the microcontroller change it when desired.
Table 11 describes the VM Register.
Table 11. VM Register
Bit 7
PIO_EN
0 = disable
PIO mode
Bit 6* Bit 5*
Bit 4
Bit 3
FL_Data Boot_Data
0 = RD
can鈥檛
access
Flash
1 = RD
access
Flash
0 = RD
can鈥檛
access
Boot Flash
1 = RD
access
Boot Flash
Bit 2
FL_Code
0 = PSEN
can鈥檛
access
Flash
Bit 1
Bit 0
Boot_Code SRAM_Code
0 = PSEN
can鈥檛
access
Boot Flash
0 = PSEN
can鈥檛
access
SRAM
1 = PSEN
access
SRAM
*
*
1= enable
PIO mode
*
*
1 = PSEN 1 = PSEN
access
access
Flash
Boot Flash
NOTE:
Bits 6-5 are not used.
29