PSD813F2 Datasheet

  • PSD813F2

  • FLASH IN-SYSTEM PROGRAMMABLE (ISP) PERIPHERALS FOR 8-BIT MCU...

  • 1180.57KB

  • STMicroelectronics   STMicroelectronics

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PSD835G2
PSD8XX Family
The
PSD835G2
Functional
Blocks
(cont.)
9.1.4 Page Register
The eight bit Page Register increases the addressing capability of the microcontroller by a
factor of up to 256. The contents of the register can also be read by the microcontroller.
The outputs of the Page Register (PGR0-PGR7) are inputs to the PLD decoder and
can be included in the Flash Memory, secondary Flash memory, and SRAM chip select
equations.
If memory paging is not needed, or if not all 8 page register bits are needed for memory
paging, then these bits may be used in the PLD for general logic. See Application
Notes.
Figure 9 shows the Page Register. The eight flip flops in the register are connected to the
internal data bus D0-D7. The microcontroller can write to or read from the Page Register.
The Page Register can be accessed at address location CSIOP + E0h.
Figure 9. Page Register
RESET
D0
D1
D0 - D7
D2
D3
D4
D5
D6
R/W
D7
Q0
Q1
Q2
Q3
Q4
Q5
PGR0
PGR1
PGR2
PGR3
PGR4
PGR5
PGR6
DPLD
AND
GPLD
INTERNAL
SELECTS
AND LOGIC
Q6
PGR7
Q7
PAGE
REGISTER
FLASH
PLD
31

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