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PSD813F2 Datasheet

  • PSD813F2

  • FLASH IN-SYSTEM PROGRAMMABLE (ISP) PERIPHERALS FOR 8-BIT MCU...

  • 1180.57KB

  • STMicroelectronics   STMicroelectronics

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PSD835G2
PSD8XX Family
The
PSD835G2
Functional
Blocks
(cont.)
9.2 PLDs
The PLDs bring programmable logic functionality to the PSD835G2. After specifying the
logic for the PLDs in PSDsoft, the logic is programmed into the device and available upon
power-up.
The PSD835G2 contains two PLDs: the Decode PLD (DPLD), and the Complex PLD
(CPLD). The PLDs are briefly discussed in the next few paragraphs, and in more detail in
sections 9.2.1 and 9.2.2. Figure 10 shows the configuration of the PLDs.
The DPLD performs address decoding for internal components, such as memory,
registers, and I/O port selects.
The CPLD can be used for logic functions, such as loadable counters and shift registers,
state machines, and encoding and decoding logic. These logic functions can be
constructed using the 16 Output Micro鈬擟ells (OMCs), 24 Input Micro鈬擟ells (IMCs), and
the AND array. The CPLD can also be used to generate external chip selects.
The AND array is used to form product terms. These product terms are specified using
PSDsoft. An Input Bus consisting of 82 signals is connected to the PLDs. The signals are
shown in Table 12.
Table 12. DPLD and CPLD Inputs
Input Source
MCU Address Bus
MCU Control Signals
Reset
Power Down
Port A Input Micro鈬擟ells
Port B Input Micro鈬擟ells
Port C Input Micro鈬擟ells
Port D Inputs
Port F Inputs
Page Register
Micro鈬擟ell A Feedback
Micro鈬擟ell B Feedback
Flash Programming Status Bit
NOTE:
The address inputs are A[19:4] in 80C51XA mode.
Input Name
A[15:0]
*
CNTL[2:0]
RST
PDN
PA[7-0]
PB[7-0]
PC[7-0]
PD[3:0]
PF[7:0]
PGR(7:0)
MCELLA.FB[7:0]
MCELLB.FB[7:0]
Rdy/Bsy
Number
of Signals
16
3
1
1
8
8
8
4
8
8
8
8
1
The Turbo Bit
The PLDs in the PSD835G2 can minimize power consumption by switching to standby
when inputs remain unchanged for an extended time of about 70 ns. Setting the Turbo
mode bit to off (Bit 3 of the PMMR0 register) automatically places the PLDs into standby if
no inputs are changing. Turbo-off mode increases propagation delays while reducing
power consumption. Refer to the Power Management Unit section on how to set the Turbo
Bit. Additionally, five bits are available in the PMMR2 register to block MCU control signals
from entering the PLDs. This reduces power consumption and can be used only when
these MCU control signals are not used in PLD logic equations.
33

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