鈬?/div>
Cell
Eight of the Output Micro鈬擟ells are connected to Port A pins are named as McellA0-7.
The other eight Micro鈬擟ells are connected to Port B pins are named as McellB0-7.
The
PSD835G2
Functional
Blocks
(cont.)
Table 13. Output Micro鈬擟ell Port and Data Bit Assignments
Native
Product
Terms
3
3
3
3
3
3
3
3
4
4
4
4
4
4
4
4
Maximum
Borrowed
Product
Terms
6
6
6
6
6
6
6
6
5
5
5
5
6
6
6
6
Data Bit for
Loading or
Reading
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
Output
Micro鈬擟ell
McellA0
McellA1
McellA2
McellA3
McellA4
McellA5
McellA6
McellA7
McellB0
McellB1
McellB2
McellB3
McellB4
McellB5
McellB6
McellB7
Port
Assignment
Port A0
Port A1
Port A2
Port A3
Port A4
Port A5
Port A6
Port A7
Port B0
Port B1
Port B2
Port B3
Port B4
Port B5
Port B6
Port B7
The Output Micro鈬擟ell (OMC) architecture is shown in Figure 13. As shown in the figure,
there are native product terms available from the AND array, and borrowed product terms
available (if unused) from other OMCs. The polarity of the product term is controlled by the
XOR gate. The OMC can implement either sequential logic, using the flip-flop element, or
combinatorial logic. The multiplexer selects between the sequential or combinatorial logic
outputs. The multiplexer output can drive a Port pin and has a feedback path to the AND
array inputs.
The flip-flop in the OMC can be configured as a D, T, JK, or SR type in the PSDsoft
program. The flip-flop鈥檚 clock, preset, and clear inputs may be driven from a product term
of the AND array. Alternatively, the external CLKIN signal can be used for the clock input
to the flip-flop. The flip-flop is clocked on the rising edge of the clock input. The preset and
clear are active-high inputs. Each clear input can use up to two product terms.
38