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PSD813F2数据手册封面

PSD813F2 Datasheet

  • PSD813F2

  • FLASH IN-SYSTEM PROGRAMMABLE (ISP) PERIPHERALS FOR 8-BIT MCU...

  • 1180.57KB

  • STMicroelectronics   STMicroelectronics

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PSD8XX Family
PSD835G2
9.4.2.3 Address Out Mode
For microcontrollers with a multiplexed address/data bus, Address Out Mode can be used
to drive latched addresses onto the port pins. These port pins can, in turn, drive external
devices. Either the output enable or the corresponding bits of both the Direction Register
and Control Register must be set to a 鈥?鈥?for pins to use Address Out Mode. This must be
done by the MCU at run-time. See Table 18 for the address output pin assignments on
Ports E, F and F for various MCUs.
Note:
Do not drive address lines with Address Out Mode to an external memory device if
it is intended for the MCU to boot from the external device. The MCU must first boot from
PSD memory so the Direction and Control register bits can be set.
The
PSD835G2
Functional
Blocks
(cont.)
Table 18. I/O Port Latched Address Output Assignments
MCU
80C51XA
80C251
(Page Mode)
All Other
Eight-Bit
Multiplexed
8-Bit
Non-Mux
Bus
Port E (3:0)
N/A
*
N/A
Port E (7:4)
Addr (7:4)
N/A
Port F (3:0)
N/A
*
N/A
Port F (7:4)
Addr (7:4)
N/A
Port G (3:0)
Addr (11:8)
Addr (11:8)
Port G (7:4)
N/A
Addr (15:12)
Addr (3:0)
Addr (7:4)
Addr (3:0)
Addr (7:4)
Addr (3:0)
Addr (7:4)
N/A
N/A
N/A
N/A
Addr (3:0)
Addr (7:4)
9.4.2.4 Address In Mode
For microcontrollers that have more than 16 address lines, the higher addresses can be
connected to Ports A, B, C, D or F and are routed as inputs to the PLDs. The address
input can be latched in the Input Micro鈬擟ell by the address strobe (ALE/AS). Any
input that is included in the DPLD equations for the Main Flash, Boot Flash, or SRAM is
considered to be an address input.
9.4.2.5 Data Port Mode
Port F can be used as a data bus port for a microcontroller with a non-multiplexed
address/data bus. The Data Port is connected to the data bus of the microcontroller. The
general I/O functions are disabled in Port F if the ports are configured as Data Port. Data
Port Mode is automatically configured in PSDsoft when a non-multiplexed bus MCU is
selected.
9.4.2.6 Peripheral I/O Mode
Peripheral I/O Mode can be used to interface with external 8-bit peripherals. In this mode,
all of Port F serves as a tri-stateable, bi-directional data buffer for the microcontroller.
Peripheral I/O Mode is enabled by setting Bit 7 of the VM Register to a 鈥?鈥? Figure 25
shows how Port A acts as a bi-directional buffer for the microcontroller data bus if
Peripheral I/O Mode is enabled. An equation for PSEL0 and/or PSEL1 must be specified in
PSDsoft. The buffer is tri-stated when PSEL 0 or 1 is not active.
9.4.2.7 JTAG ISP
Port E is JTAG compliant, and can be used for In-System Programming (ISP). You can
multiplex JTAG operations with other functions on Port E because ISP is not performed
during normal system operation. For more information on the JTAG Port, refer to
section 9.6.
56

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