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PSD813F2数据手册封面

PSD813F2 Datasheet

  • PSD813F2

  • FLASH IN-SYSTEM PROGRAMMABLE (ISP) PERIPHERALS FOR 8-BIT MCU...

  • 1180.57KB

  • STMicroelectronics   STMicroelectronics

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PSD8XX Family
PSD835G2
The
PSD835G2
Functional
Blocks
(cont.)
9.4.6 Port D 鈥?Functionality and Structure
Port D has four I/O pins. See Figure 27. Port D can be configured to program one more of
the following functions:
t
MCU I/O Mode
t
CPLD Input 鈥?direct input to CPLD, no Input Micro鈬擟ells
Port D pins can be configured in PSDsoft as input pins for other dedicated functions:
t
PD0 鈥?ALE, as address strobe input
t
PD1 鈥?CLKIN, as clock input to the Micro鈬擟ells Flip Flops and APD counter
t
PD2 鈥?CSI, as active low chip select input. A high input will disable the
Flash/SRAM and CSIOP.
t
PD3 鈥?as DBE input from 68HC912
9.4.7 Port E 鈥?Functionality and Structure
Port E can be configured to perform one or more of the following functions (see Figure 28):
t
MCU I/O Mode
t
In-System Programming 鈥?JTAG port can be enabled for programming/erase of the
PSD8XX device. (See Section 9.6 for more information on JTAG programming.)
t
Open Drain 鈥?Port E pins can be configured in Open Drain Mode
t
Battery Backup features 鈥?PE6 can be configured as a Battery Input (Vstby) pin.
PE7 can be configured as a Battery On Indicator output
pin, indicating when Vcc is less than Vbat.
t
Latched Address Output 鈥?Provided latched address (A7-0) output
Figure 27. Port D Structure
DATA OUT
REG.
DATA OUT
D
WR
OUTPUT
MUX
Q
PORT D PIN
INTERNAL DATA BUS
READ MUX
P
D
B
DATA IN
OUTPUT
SELECT
DIR REG.
D
WR
Q
CPLD - INPUT
62

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