by setting the appropriate bits in the PMMR registers. The blocked signals include
MCU control signals and the common clock (CLKIN). Note that blocking CLKIN from
the PLDs will not block CLKIN from the APD unit.
鈥?/div>
All PSD memories enter Standby Mode and are drawing standby current. However,
the PLDs and I/O ports do
not
go into Standby Mode because you don鈥檛 want to
have to wait for the logic and I/O to 鈥渨ake-up鈥?before their outputs can change. See
Table 25 for Power Down Mode effects on PSD ports.
鈥?/div>
Typical standby current is 50 碌A for 5 V parts. This standby current value assumes
that there are no transitions on any PLD input.
Table 25. Power Down Mode鈥檚 Effect on
Ports
Port Function
MCU I/O
PLD Out
Address Out
Data Port
Peripheral I/O
Pin Level
No Change
No Change
Undefined
Three-State
Three-State
Table 26. PSD835G2 Timing and Standby Current During Power
Down Mode
PLD
Propagation
Delay
Normal tpd
(Note 1)
Mode
Power Down
Memory
Access
Time
No Access
Access
Recovery Time
to Normal
Access
tLVDV
5V V
CC
,
Typical
Standby
Current
50 碌A
(Note 2)
NOTES:
1. Power Down does not affect the operation of the PLD. The PLD operation in this
mode is based only on the Turbo Bit.
2. Typical current consumption assuming no PLD inputs are changing state and
the PLD Turbo bit is off.
65
prev
next