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PSD813F2数据手册封面

PSD813F2 Datasheet

  • PSD813F2

  • FLASH IN-SYSTEM PROGRAMMABLE (ISP) PERIPHERALS FOR 8-BIT MCU...

  • 1180.57KB

  • STMicroelectronics   STMicroelectronics

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PSD835G2
PSD8XX Family
The
PSD835G2
Functional
Blocks
(cont.)
Table 27. Power Management Mode Registers (PMMR0, PMMR2)**
PMMR0
Bit 7
Bit 6
Bit 5
PLD
Mcell clk
1 = off
Bit 4
PLD
Array clk
1 = off
Bit 3
PLD
Turbo
1 = off
Bit 2
Bit 1
APD
Enable
1 = on
Bit 0
*
*
*
*
***
Bits 0, 2, 6, and 7 are not used, and should be set to 0.
***
The PMMR0, and PMMR2 register bits are cleared to zero following power up.
***
Subsequent reset pulses will not clear the registers.
Bit 1 0
1
Bit 3 0
1
Bit 4 0
Automatic Power Down (APD) is disabled.
Automatic Power Down (APD) is enabled.
PLD Turbo is on.
PLD Turbo is off, saving power.
CLKIN input to the PLD AND array is connected.
Every CLKIN change will power up the PLD when Turbo bit is off.
1 = CLKIN input to PLD AND array is disconnected, saving power.
Bit 5 0 = CLKIN input to the PLD Micro鈬擟ells is connected.
1 = CLKIN input to PLD Micro鈬擟ells is disconnected, saving power.
PMMR2
Bit 7
*
Bit 6
PLD
array
DBE
1 = off
=
=
=
=
=
Bit 5
PLD
array
ALE
1 = off
Bit 4
PLD
**
array
CNTL2
1 = off
Bit 3
PLD
**
array
CNTL1
1 = off
Bit 2
PLD
**
array
CNTL0
1 = off
Bit 1
*
Bit 0
PLD
array
Addr.
1 = off
**
Unused bits should be set to 0.
**
Refer to Table 14 the signals that are blocked on pins CNTL0-2.
Bit 0 0 = Address A[7:0] inputs to the PLD AND array are connected.
1 = Address A[7:0] inputs to the PLD AND array are disconnected, saving power.
Note:
In 80C51 mode, A[7:1] comes from Port F (PF1-PF3) and AD10 [3:0].
Bit 2 0 = Cntl0 input to the PLD AND array is connected.
1 = Cntl0 input to PLD AND array is disconnected, saving power.
Bit 3 0 = Cntl1 input to the PLD AND array is connected.
1 = Cntl1 input to PLD AND array is disconnected, saving power.
Bit 4 0 = Cntl2 input to the PLD AND array is connected.
1 = Cntl2 input to PLD AND array is disconnected, saving power.
Bit 5 0 = ALE input to the PLD AND array is connected.
1 = ALE input to PLD AND array is disconnected, saving power.
Bit 6 0 = DBE input to the PLD AND array is connected.
1 = DBE input to PLD AND array is disconnected, saving power.
67

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