您的位置：维库电子市场网 > Datasheet > PSD813F2
PSD813F2数据手册封面

PSD813F2 Datasheet

  • PSD813F2

  • FLASH IN-SYSTEM PROGRAMMABLE (ISP) PERIPHERALS FOR 8-BIT MCU...

  • 1180.57KB

  • STMicroelectronics   STMicroelectronics

阅览下载 纠错 0

扫码查看芯片数据手册

上传产品规格书

PDF预览

PSD8XX Family
PSD835G2
PSD8XX
Architectural
Overview
(cont.)
4.5 ISP via JTAG Port
In-System Programming can be performed through the JTAG pins on Port E. This serial
interface allows complete programming of the entire PSD835G2 device. A blank device
can be completely programmed. The JTAG signals (TMS, TCK, TSTAT, TERR, TDI, TDO)
can be multiplexed with other functions on Port E. Table 3 indicates the JTAG signals pin
assignments.
4.6 In-System Programming (ISP)
Using the JTAG signals on Port E, the entire PSD835G2 (memory, logic, configuration)
device can be programmed or erased without the use of the microcontroller.
Table 3. JTAG Signals on Port E
Port E Pins
PE0
PE1
PE2
PE3
PE4
PE5
JTAG Signal
TMS
TCK
TDI
TDO
TSTAT
TERR
4.7 In-Application re-Programming (IAP)
The main Flash memory can also be programmed in-system by the microcontroller
executing the programming algorithms out of the secondary Flash memory, or SRAM.
Since this is a sizable separate block, the application can also continue to operate. The
secondary Flash boot memory can be programmed the same way by executing out of the
main Flash memory. Table 4 indicates which programming methods can program different
functional blocks of the PSD8XX.
Table 4. Methods of Programming Different Functional Blocks of the PSD835G2
Functional Block
Main Flash memory
Flash Boot memory
PLD Array (DPLD and CPLD)
PSD Configuration
JTAG-ISP
Yes
Yes
Yes
Yes
Device
Programmer
Yes
Yes
Yes
Yes
IAP
Yes
Yes
No
No
4.8 Page Register
The eight-bit Page Register expands the address range of the microcontroller by up to
256 times.The paged address can be used as part of the address space to access
external memory and peripherals or internal memory and I/O. The Page Register can also
be used to change the address mapping of blocks of Flash memory into different memory
spaces for IAP.
4.9 Power Management Unit
The Power Management Unit (PMU) in the PSD835G2 gives the user control of the
power consumption on selected functional blocks based on system requirements. The
PMU includes an Automatic Power Down unit (APD) that will turn off device functions due
to microcontroller inactivity. The APD unit has a Power Down Mode that helps reduce
power consumption.
The PSD835G2 also has some bits that are configured at run-time by the MCU to reduce
power consumption of the CPLD. The turbo bit in the PMMR0 register can be turned off
and the CPLD will latch its outputs and go to standby until the next transition on its inputs.
Additionally, bits in the PMMR2 register can be set by the MCU to block signals from
entering the CPLD to reduce power consumption. See section 9.5.
6

PSD813F2 PDF文件相关型号

PSD813F2V,PSD813F3,PSD813F3V,PSD813F4,PSD813F4V,PSD813F5,PSD813F5V,PSD833F2V,PSD854F2,PSD854F2V

PSD813F2相关型号PDF文件下载

您可能感兴趣的PDF文件资料

热门IC型号推荐

©2024 维库电子市场网（www.dzsc.com）　备案号：浙B2-20050339-1 经营许可证：浙B2-20210386版权声明
买家服务热线：0571-85317607 | 买家服务部QQ： QQ:1609526468
卖家服务热线：0571-85317607 | 卖家服务部QQ： QQ:331652727

扫码下载APP，
一键连接广大的电子世界。

在线人工客服

买家服务：
卖家服务：
技术客服：

0571-85317607

网站技术支持

13588313025

客服在线时间周一至周五
9:00-17:30

关注官方微信号，
第一时间获取资讯。

建议反馈
返回顶部

建议反馈

联系人：

联系方式：

按住滑块，拖拽到最右边
>>
感谢您向阿库提出的宝贵意见，您的参与是维库提升服务的动力！意见一经采纳，将有感恩红包奉上哦！

PDF纠错X

投诉电话：0571-85317607 投诉QQ：

如选匿名将无法为您反馈投诉结果，建议实名投诉！