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PSD813F2数据手册封面

PSD813F2 Datasheet

  • PSD813F2

  • FLASH IN-SYSTEM PROGRAMMABLE (ISP) PERIPHERALS FOR 8-BIT MCU...

  • 1180.57KB

  • STMicroelectronics   STMicroelectronics

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PSD8XX Family
PSD835G2
The
PSD835G2
Functional
Blocks
(cont.)
9.6.1 Standard JTAG Signals (cont.)
The PSD835G2 supports JTAG-ISP commands, but not Boundary Scan. ST's
PSDsoft software tool and FlashLink JTAG programming cable implement these JTAG-ISC
commands.
9.6.2 JTAG Extensions
TSTAT and TERR are two JTAG extension signals enabled by a JTAG command
received over the four standard JTAG pins (TMS, TCK, TDI, and TDO). They are used to
speed programming and erase functions by indicating status on PSD pins instead of
having to scan the status out serially using the standard JTAG channel. See Application
Note 54.
TERR will indicate if an error has occurred when erasing a sector or programming in
Flash memory. This signal will go low (active) when an error condition occurs, and stay
low until a special JTAG command is executed or a chip reset pulse is received after an
鈥淚SC-DISABLE鈥?command.
TSTAT behaves the same as the Rdy/Bsy signal described in section 9.1.1.2. TSTAT will
be high when the PSD835G2 device is in read array mode (Flash memory and Boot Block
contents can be read). TSTAT will be low when Flash memory programming or erase
cycles are in progress, and also when data is being written to the Flash Boot Block.
TSTAT and TERR can be configured as open-drain type signals with a JTAG command.
9.6.3 Security and Flash Memories Protection
When the security bit is set, the device cannot be read on a device programmer or through
the JTAG Port. When using the JTAG Port, only a full chip erase command is allowed.
All other program/erase/verify commands are blocked. Full chip erase returns the part to a
non-secured blank state. The Security Bit can be set in PSDsoft.
All Flash Memory and Boot sectors can individually be sector protected against erasures.
The sector protect bits can be set in PSDsoft.
72

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