PSD835G2
PSD8XX Family
Microcontroller Interface 鈥?PSD835G2 AC/DC Parameters
(5V 卤 10% Versions)
Port F Peripheral Data Mode Read Timing
(5 V 卤 10%)
-70
Symbol
t
AVQV (PF)
t
SLQV (PF)
t
RLQV (PF)
t
DVQV (PF)
t
QXRH (PF)
t
RLRH (PF)
t
RHQZ (PF)
-90
Min
Max
35
35
32
38
30
0
32
23
25
Parameter
Address Valid to Data Valid
CSI Valid to Data Valid
RD to Data Valid
RD to Data Valid 8031 Mode
Data In to Data Out Valid
RD Data Hold Time
RD Pulse Width
RD to Data High-Z
Conditions
(Note 3)
Min
Max
30
25
Turbo
Off
Add 12
Add 12
Unit
ns
ns
ns
ns
ns
ns
ns
ns
(Notes 1 and 4)
21
31
22
0
(Note 1)
(Note 1)
27
Port F Peripheral Data Mode Write Timing
(5 V 卤 10%)
-70
Symbol
t
WLQV (PF)
t
DVQV (PF)
t
WHQZ (PF)
NOTES:
1.
2.
3.
4.
5.
-90
Min
Max
35
30
25
Parameter
WR to Data Propagation Delay
Data to Port F Data Propagation Delay
WR Invalid to Port F Tri-state
Conditions
(Note 2)
(Note 5)
(Note 2)
Min
Max
25
22
20
Unit
ns
ns
ns
RD timing has the same timing as DS and PSEN signals.
WR timing has the same timing as E and DS signals.
Any input used to select Port F Data Peripheral Mode.
Data is already stable on Port F.
Data stable on ADIO pins to data on Port F.
83