PSD835G2
PSD8XX Family
PSD835G2 AC/DC Parameters 鈥?CPLD Timing Parameters
(3.0 V to 3.6 V Versions)
GPLD Combinatorial Timing
(3.0 V to 3.6 V Versions)
-90
Symbol
t
PD
t
EA
t
ER
t
ARP
t
ARPW
t
ARD
-12
Min
Max
43
45
45
43
30
23
27
Add 4
Parameter
GPLD Input Pin/Feedback to
GPLD Combinatorial Output
GPLD Input to GPLD Output
Enable
GPLD Input to GPLD Output
Disable
GPLD Register Clear or
Preset Delay
GPLD Register Clear or
Preset Pulse Width
GPLD Array Delay
Conditions
Min
Max
38
43
43
38
PT
Aloc
TURBO
OFF
Slew
Rate
(Note 1)
Unit
ns
ns
ns
ns
ns
ns
Add 4 Add 20 Sub 6
Add 20 Sub 6
Add 20 Sub 6
Add 20 Sub 6
Add 20
28
Any Micro鈬擟ell
NOTE:
1. Fast Slew Rate output available on Port C and F.
GPLD Micro
鈬?/div>
Cell Synchronous Clock Mode Timing
(3.0 V to 3.6 V Versions)
-90
-12
PT
Aloc
TURBO
OFF
Slew
Rate
(Note 1)
Symbol
Parameter
Maximum Frequency
External Feedback
Conditions
1/(t
S
+ t
CO
)
1/(t
S
+ t
CO
鈥?0)
1/(t
C H
+ t
CL
)
Min
Max
24.3
32.2
45.0
Min
Max
20.4
25.6
35.7
Unit
MHz
MHz
MHz
f
MAX
Maximum Frequency
Internal Feedback ( f
CNT
)
Maximum Frequency
Pipelined Data
t
S
t
H
t
CH
t
CL
t
CO
t
ARD
t
MIN
Input Setup Time
Input Hold Time
Clock High Time
Clock Low Time
Clock to Output Delay
GPLD Array Delay
Minimum Clock Period
Clock Input
Clock Input
Clock Input
Any Micro鈬擟ell
t
C H
+ t
CL
(Note 2)
18
0
11
11
23
23
22
23
0
14
14
26
27
28
Add 4 Add 20
ns
ns
ns
ns
Sub 6
ns
ns
ns
Add 4
NOTES:
1. Fast Slew Rate output available on Port C and F.
2. CLKIN t
CLCL
= t
CH
+ t
CL
.
87
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