PSD813F2 Datasheet

  • PSD813F2

  • FLASH IN-SYSTEM PROGRAMMABLE (ISP) PERIPHERALS FOR 8-BIT MCU...

  • 1180.57KB

  • STMicroelectronics   STMicroelectronics

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PSD8XX Family
PSD835G2
PSD835G2 AC/DC Parameters 鈥?GPLD Timing Parameters
(3.0 V to 3.6 V Versions)
GPLD Micro
鈬?/div>
Cell Asynchronous Clock Mode Timing
(3.0 V to 3.6 V Versions)
-90
Symbol
Parameter
Maximum Frequency
External Feedback
f
MAXA
Maximum Frequency
Internal Feedback ( f
CNTA
)
Maximum Frequency
Pipelined Data
t
SA
t
HA
t
CHA
t
CLA
t
COA
t
ARD
t
MINA
Input Setup Time
Input Hold Time
Clock High Time
Clock Low Time
Clock to Output Delay
GPLD Array Delay
Minimum Clock Period
Any Micro鈬擟ell
1/ f
C NTA
32
-12
Min
Max
20.8
26.3
30.3
10
12
18
15
34
23
38
38
27
Add 4
Add 20
Add 20
Add 20 Sub 6
Add 4 Add 20
Conditions
1/(t
S A
+ t
CO A
)
1/(t
S A
+ t
CO A
鈥?0)
1/(t
C H A
+ t
CLA
)
Min
Max
23.8
31.25
38.4
PT
Aloc
TURBO
OFF
Slew
Rate
Unit
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
8
10
15
12
Input Micro
鈬?/div>
Cell Timing
(3.0 V to 3.6 V Versions)
-90
Symbol
t
IS
t
IH
t
INH
t
IN L
t
INO
-12
Min
0
23
13
13
46
62
Add 4
Add 20
Add 20
Parameter
Input Setup Time
Input Hold Time
NIB Input High Time
NIB Input Low Time
NIB Input to Combinatorial
Delay
Conditions
(Note 1)
(Note 1)
(Note 1)
(Note 1)
(Note 1)
Min
0
20
13
12
Max
Max
PT
Aloc
TURBO
OFF
Unit
ns
ns
ns
ns
ns
NOTE:
1. Inputs from Port A, B, and C relative to register/latch clock from the PLD. ALE latch timings refer to t
AVLX
and t
LXAX
.
88

PSD813F2 PDF文件相关型号

PSD813F2V,PSD813F3,PSD813F3V,PSD813F4,PSD813F4V,PSD813F5,PSD813F5V,PSD833F2V,PSD854F2,PSD854F2V

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