PSD835G2
PSD8XX Family
Microcontroller Interface 鈥?PSD835G2 AC/DC Parameters
(3.0 V to 3.6 V Versions)
Power Down Timing
(3.0 V to 3.6 V Versions)
-90
Symbol
t
LVDV
t
CLWH
-12
Min
Max
135
Parameter
ALE Access Time from
Power Down
Maximum Delay from APD Enable
to Internal PDN Valid Signal
Conditions
Min
Max
128
Unit
ns
碌s
Using CLKIN Input
15
*
t
CLCL
(碌s) (Note 1)
NOTE:
1. t
CLCL
is the CLKIN clock period.
V
stbyon
Timing
(3.0 V to 3.6 V Versions)
Symbol
t
BVBH
t
BXBL
Parameter
Vstby Detection to Vstbyon Output
High
Vstby Off Detection to Vstbyon
Output Low
Conditions
(Note 1)
(Note 1)
Min
Typ
20
20
Max
Unit
碌s
碌s
NOTE:
1. Vstbyon is measured at V
CC
ramp rate of 2 ms.
Reset Pin Timing
(3.0 V to 3.6 V Versions)
Symbol
t
NLNH
t
OPR
t
NLNH-PO
t
NLNH-A
Parameter
Warm RESET Active Low Time (Note 1)
RESET High to Operational Device
Power On Reset Active Low Time
Warm RESETActive Low Time
(Note 2)
Conditions
Min
300
Typ
Max
Unit
ns
300
1
25
ns
ms
碌s
NOTE:
1. RESET will not abort Flash programming/erase cycles.
2. RESET will abort Flash programming or erase cycle.
93