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IDT71V547 Datasheet

  • IDT71V547

  • 128K X 36, 3.3V Synchronous SRAM with ZBT? Feature, Burst Co...

  • 162.40KB

  • IDT

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IDT71V547, 128K x 36, 3.3V Synchronous SRAM with
ZBT鈩?Feature, Burst Counter and Flow-Through Outputs
鈩?/div>
Commercial and Industrial Temperature Ranges
Read Operation with Chip Enable Used
(1)
Cycle
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
n+9
Address
X
X
A0
X
A1
X
X
A2
X
X
R/W
X
X
H
X
H
X
X
H
X
X
ADV/LD
L
L
L
L
L
L
L
L
L
L
CE
(1)
H
H
L
H
L
H
H
L
H
H
CEN
L
L
L
L
L
L
L
L
L
L
BW
x
X
X
X
X
X
X
X
X
X
X
OE
X
X
X
L
X
L
X
X
L
X
I/O
(3)
?
Z
Z
Q0
Z
Q1
Z
Z
Q2
Z
Deselected
Deselected
Address A0 and Control meet setup
Address A0 read out. Deselected
Address A1 and Control meet setup
Address A1 Read out. Deselected
Deselected
Address A2 and Control meet setup
Address A2 read out. Deselected
Deselected
3822 tbl 18
Comments
NOTES:
1. H = High; L = Low; X = Don鈥檛 Care; ? = Don't Know; Z = High Impedance.
2.
CE
2
timing transition is identical to
CE
1
signal. CE
2
timing transition is identical but inverted to the
CE
1
and
CE
2
signals.
3. Device outputs are ensured to be in High-Z during device power-up.
Write Operation with Chip Enable Used
(1)
Cycle
n
n+ 1
n+ 2
n+ 3
n+ 4
n+ 5
n+ 6
n+ 7
n+ 8
n+ 9
Address
X
X
A0
X
A1
X
X
A2
X
X
R/W
X
X
L
X
L
X
X
L
X
X
ADV/LD
L
L
L
L
L
L
L
L
L
L
CE
(1 )
H
H
L
H
L
H
H
L
H
H
CEN
L
L
L
L
L
L
L
L
L
L
BW
x
X
X
L
X
L
X
X
L
X
X
OE
X
X
X
X
X
X
X
X
X
X
I/O
?
Z
Z
D0
Z
D1
Z
Z
D2
Z
D eselected
D eselected
Address A 0 and Control m eet setup
Addres s D0 W rite In. D eselected
Address A 1 and Control m eet setup
Addres s D1 W rite In. D eselected
D eselected
Address A 2 and Control m eet setup
Addres s D2 W rite In. D eselected
D eselected
3822 tbl 19
Comments
NOTES:
1. H = High; L = Low; X = Don鈥檛 Care; ? = Don't Know; Z = High Impedance.
2.
CE
= L is defined as
CE
1
= L,
CE
2
= L and CE
2
= H.
CE
= H is defined as
CE
1
= H,
CE
2
= H or CE
2
= L.
10

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