ZBT鈩?Feature, Burst Counter and Flow-Through Outputs
鈩?/div>
Commercial and Industrial Temperature Ranges
Interleaved Burst Sequence Table (LBO=V
DD
)
Sequence 1
A1
First Address
Second Address
Third Address
Fourth Address
(1)
0
0
1
1
A0
0
1
0
1
Sequence 2
A1
0
0
1
1
A0
1
0
1
0
Sequence 3
A1
1
1
0
0
A0
0
1
0
1
Sequence 4
A1
1
1
0
0
A0
1
0
1
0
3822 tbl 09
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
Linear Burst Sequence Table (LBO=V
SS
)
Sequence 1
A1
First Address
Second Address
Third Address
Fourth Address
(1)
0
0
1
1
A0
0
1
0
1
Sequence 2
A1
0
1
1
0
A0
1
0
1
0
Sequence 3
A1
1
1
0
0
A0
0
1
0
1
Sequence 4
A1
1
0
0
1
A0
1
0
1
0
3822 tbl 10
NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.
Functional Timing Diagram
(1)
CYCLE
CLOCK
ADDRESS
(A0 - A16)
(2)
A29
A30
A31
A32
A33
A34
A35
A36
A37
n+29
n+30
n+31
n+32
n+33
n+34
n+35
n+36
n+37
(2)
CONTROL
(R/W , ADV/LD,
BW
x)
(2)
DATA
I/O [0:31], I/O P[1:4]
C29
C30
C31
C32
C33
C34
C35
C36
C37
D/Q28
D/Q29
D/Q30
D/Q31
D/Q32
D/Q33
D/Q34
D/Q35
D/Q36
.,
NOTE:
1. This assumes
CEN, CE
1
, CE2 and
CE
2
are all true.
2. All Address, Control and Data_In are only required to meet set-up and hold time with respect to the rising edge of clock. Data_Out is valid after a clock-to-data
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
