IDT71V547, 128K x 36, 3.3V Synchronous SRAM with
ZBT鈩?Feature, Burst Counter and Flow-Through Outputs
鈩?/div>
Commercial and Industrial Temperature Ranges
Device Operation - Showing Mixed Load, Burst,
Deselect and NOOP Cycles
(2)
Cycle
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
n+8
n+9
n+10
n+11
n+12
n+13
n+14
n+15
n+16
n+17
n+18
n+19
Address
A0
X
A1
X
X
A2
X
X
A3
X
A4
X
X
A5
A6
A7
X
A8
X
A9
R/W
H
X
H
X
X
H
X
X
L
X
L
X
X
L
H
L
X
H
X
L
ADV/LD
L
H
L
L
H
L
H
L
L
H
L
L
H
L
L
L
H
L
H
L
CE
(1)
L
X
L
H
X
L
X
H
L
X
L
H
X
L
L
L
X
L
X
L
CEN
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
BW
x
X
X
X
X
X
X
X
X
L
L
L
X
X
L
X
L
L
X
X
L
OE
X
L
L
L
X
X
L
L
X
X
X
X
X
X
X
L
X
X
L
L
I/O
D1
Q0
Q
0+1
Q1
Z
Z
Q2
Q
2+1
Z
D3
D
3+1
D4
Z
Z
D5
Q6
D7
D
7+1
Q8
Q
8+1
Load read
Burst read
Load read
Deselect or STOP
NOOP
Load read
Burst read
Deselect or STOP
Load write
Burst write
Load write
Deselect or STOP
NOOP
Load write
Load read
Load write
Burst write
Load read
Burst read
Load write
3822 tbl 11
Comments
NOTE:
1.
CE
2
timing transition is identical to
CE
1
signal. CE
2
timing transition is identical but inverted to the
CE
1
and
CE
2
signals.
2. H = High; L = Low; X = Don't Care; Z = High Impedence.
7
6.42
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