FOR
FOR
CY7C68001
11.5
Slave FIFO Output Enable
SLOE
t
OEoff
Following timings are applicable to synchronous and asynchronous interfaces.
DATA
t
OEon
Figure 11-14. Slave FIFO Output Enable Timing Diagram
[11]
Table 11-19. Slave FIFO Output Enable Parameters
Parameter
t
OEon
t
OEoff
Description
SLOE assert to FIFO DATA Output
SLOE deassert to FIFO DATA Hold
Min.
Max.
10.5
10.5
Unit
ns
ns
11.6
11.6.1
Sequence Diagram
Single and Burst Synchronous Read Example
t
IFCLK
IFCLK
t
SFA
t
FAH
t
SFA
t
FAH
FIFOADR
t=0
t
SRD
t
RDH
T=0
>= t
SRD
>= t
RDH
SLRD
t=2
t=3
T=2
T=3
SLCS
t
XFLG
FLAGS
t
XFD
t
XFD
N+1
t
OEoff
t
OEon
N+1
N+2
t
XFD
N+3
t
XFD
N+4
DATA
Data Driven: N
t
OEon
t
OEoff
SLOE
t=1
t=4
T=1
T=4
Figure 11-15. Slave FIFO Synchronous Read Sequence and Timing Diagram
IFCLK
IFCLK
IFCLK
IFCLK
IFCLK
IFCLK
IFCLK
IFCLK
IFCLK
IFCLK
FIFO POINTER
N
SLOE
N
SLRD
N+1
SLOE
SLRD
N+1
SLOE
N+1
SLRD
N+2
N+2
N+3
N+3
N+4
SLRD
N+4
SLO E
N+4
Not Driven
FIFO DATA BUS
Not Driven
Driven: N
N+1
Not Driven
N+1
N+4
N+4
Figure 11-16. Slave FIFO Synchronous Sequence of Events Diagram
Document #: 38-08013 Rev. *E
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