您的位置：维库电子市场网 > Datasheet > CY7C68001
CY7C68001数据手册封面

CY7C68001 Datasheet

  • CY7C68001

  • IC,BUS CONTROLLER,SSOP,56PIN

  • 612.03KB

  • cypress

阅览下载 纠错 0

扫码查看芯片数据手册

上传产品规格书

PDF预览

FOR
FOR
CY7C68001
Figure 11-15
shows the timing relationship of the SLAVE FIFO
signals during a synchronous FIFO read using IFCLK as the
synchronizing clock. The diagram illustrates a single read
followed by a burst read.
鈥?At t = 0 the FIFO address is stable and the signal SLCS is
asserted (SLCS may be tied low in some applications).
Note: t
SFA
has a minimum of 25 nsec. This means when
IFCLK is running at 48 MHz, the FIFO address setup time
is more than one IFCLK cycle.
鈥?At = 1, SLOE is asserted. SLOE is an output enable only,
whose sole function is to drive the data bus. The data that
is driven on the bus is the data that the internal FIFO pointer
is currently pointing to. In this example it is the first data
value in the FIFO. Note: the data is pre-fetched and is driven
on the bus when SLOE is asserted.
鈥?At t = 2, SLRD is asserted. SLRD must meet the setup time
of t
SRD
(time from asserting the SLRD signal to the rising
edge of the IFCLK) and maintain a minimum hold time of
t
RDH
(time from the IFCLK edge to the deassertion of the
SLRD signal). If the SLCS signal is used, it must be asserted
with SLRD, or before SLRD is asserted (i.e. the SLCS and
SLRD signals must both be asserted to start a valid read
condition).
鈥?The FIFO pointer is updated on the rising edge of the IFCLK,
while SLRD is asserted. This starts the propagation of data
from the newly addressed location to the data bus. After a
propagation delay of t
XFD
(measured from the rising edge
of IFCLK) the new data value is present. N is the first data
value read from the FIFO. In order to have data on the FIFO
data bus, SLOE MUST also be asserted.
The same sequence of events are shown for a burst read and
are marked with the time indicators of T = 0 through 5. Note:
For the burst mode, the SLRD and SLOE are left asserted
during the entire duration of the read. In the burst read mode,
when SLOE is asserted, data indexed by the FIFO pointer is
on the data bus. During the first read cycle, on the rising edge
of the clock the FIFO pointer is updated and increments to
point to address N+1. For each subsequent rising edge of
IFCLK, while the SLRD is asserted, the FIFO pointer is incre-
mented and the next data value is placed on the data bus.
11.6.2
Single and Burst Synchronous Write
t
IFCLK
IFCLK
t
SFA
t
FAH
t
SFA
t
FAH
FIFOADR
t=0
t
SWR
t
WRH
T=0
>= t
SWR
>= t
WRH
SLWR
t=2
t=3
T=2
T=5
SLCS
t
XFLG
t
XFLG
FLAGS
t
SFD
t
FDH
N
t=1
T=1
t
SFD
N+1
t
FDH
t
SFD
N+2
t
FDH
t
SFD
N+3
T=4
t
FDH
DATA
T=3
t
SPE
t
PEH
PKTEND
Figure 11-17. Slave FIFO Synchronous Write Sequence and Timing Diagram
[12]
Figure 11-17
shows the timing relationship of the SLAVE FIFO
signals during a synchronous write using IFCLK as the
synchronizing clock. The diagram illustrates a single write
followed by burst write of 3 bytes and committing all 4 bytes as
a short packet using the PKTEND pin.
鈥?At t = 0 the FIFO address is stable and the signal SLCS is
asserted. (SLCS may be tied low in some applications)
Note: t
SFA
has a minimum of 25 ns. This means when IFCLK
is running at 48 MHz, the FIFO address setup time is more
than one IFCLK cycle.
鈥?At t = 1, the external master/peripheral must outputs the
data value onto the data bus with a minimum set up time of
t
SFD
before the rising edge of IFCLK.
鈥?At t = 2, SLWR is asserted. The SLWR must meet the setup
time of t
SWR
(time from asserting the SLWR signal to the
rising edge of IFCLK) and maintain a minimum hold time of
t
WRH
(time from the IFCLK edge to the de-assertion of the
SLWR signal). If SLCS signal is used, it must be asserted
with SLWR or before SLWR is asserted. (i.e. the SLCS and
SLWR signals must both be asserted to start a valid write
condition).
Page 32 of 42
Document #: 38-08013 Rev. *E

CY7C68001相关型号PDF文件下载

您可能感兴趣的PDF文件资料

热门IC型号推荐

©2024 维库电子市场网（www.dzsc.com）　备案号：浙B2-20050339-1 经营许可证：浙B2-20210386版权声明
买家服务热线：0571-85317607 | 买家服务部QQ： QQ:1609526468
卖家服务热线：0571-85317607 | 卖家服务部QQ： QQ:331652727

扫码下载APP，
一键连接广大的电子世界。

在线人工客服

买家服务：
卖家服务：

0571-85317607

客服在线时间周一至周五
9:00-17:30

关注官方微信号，
第一时间获取资讯。

建议反馈
返回顶部

建议反馈

联系人：

联系方式：

按住滑块，拖拽到最右边
>>
感谢您向阿库提出的宝贵意见，您的参与是维库提升服务的动力！意见一经采纳，将有感恩红包奉上哦！

PDF纠错X

投诉电话：0571-85317607 投诉QQ：

如选匿名将无法为您反馈投诉结果，建议实名投诉！