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CY7C68001数据手册封面

CY7C68001 Datasheet

  • CY7C68001

  • IC,BUS CONTROLLER,SSOP,56PIN

  • 612.03KB

  • cypress

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FOR
FOR
CY7C68001
or resuming or that a self-powered device has been plugged
in or unplugged. If the
SX2
is bus-powered, the external
master must put the
SX2
into a low-power mode after
detecting a USB suspend condition to be USB-compliant.
Bit 0: READY
If this interrupt is enabled, bit 0 in the Interrupt Status Byte is
set when the
SX2
has powered up and performed a self-test.
The external master should always wait for this interrupt
before trying to read or write to the
SX2,
unless an external
EEPROM with a valid descriptor is present. If an external
EEPROM with a valid descriptor is present, the ENUMOK
interrupt will occur instead of the READY interrupt after power
up. A READY interrupt will also occur if the
SX2
is awakened
from a low-power mode via the WAKEUP pin. This READY
interrupt indicates that the
SX2
is ready for commands or data.
Although it is true that all interrupts will be buffered once a
command read request has been initiated, in very rare condi-
tions, there might be a situation when there is a pending
interrupt already, when a read request is initiated by the
external master. In this case it is the interrupt status byte that
will be output when the external master asserts the SLRD. So,
a condition exists where the Interrupt Status Data Byte can be
mistaken for the result of a command register read request. In
order to get around this possible race condition, the first thing
that the external master must do on getting an interrupt from
the
SX2
is check the status of the READY pin. If the READY
is low at the time the INT# was asserted, the data that will be
output when the external master strobes the SLRD is the
interrupt status byte (not the actual data requested). If the
READY pin is high at the time when the interrupt is asserted,
the data output on strobing the SLRD is the actual data byte
requested by the external master. So it is important that the
state of the READY pin be checked at the time the INT# is
asserted to ascertain the cause of the interrupt.
RESET# signal. The Clock must be in a stable state for at least
200 us before the RESET is released.
3.5.2
USB Reset
When the
SX2
detects a USB Reset condition on the USB bus,
SX2
handles it like any other enumeration sequence. This
means that
SX2
will enumerate again and assert the
ENUMOK interrupt to let the external master know that it has
enumerated. The external master will then be responsible for
configuring the
SX2
for the application. The external master
should also check whether
SX2
enumerated at High or Full
speed in order to adjust the EPxPKTLENH/L register values
accordingly. The last initialization task is for the external
master to flush all of the
SX2
FIFOs.
3.5.3
Wakeup
The
SX2
exits its low-power state when one of the following
events occur:
鈥?USB bus signals a resume. The
SX2
will assert a BUSAC-
TIVITY interrupt.
鈥?The external master asserts the WAKEUP pin. The
SX2
will
assert a READY interrupt
[3]
.
3.6
3.6.1
Endpoint RAM
Size
鈥?Control endpoint: 64 Bytes: 1 脳 64 bytes (Endpoint 0).
鈥?FIFO Endpoints: 4096 Bytes: 8 脳 512 bytes (Endpoint 2, 4,
6, 8).
3.6.2
Organization
鈥?EP0鈥揃idirectional Endpoint 0, 64-byte buffer.
3.5
3.5.1
Resets and Wakeup
Reset
An input pin (RESET#) resets the chip. The internal PLL stabi-
lizes after V
CC
has reached 3.3V. Typically, an external RC
network (R = 100 K Ohms, C = 0.1 uf) is used to provide the
鈥?EP2, 4, 6, 8鈥揈ight 512-byte buffers, bulk, interrupt, or iso-
chronous. EP2 and EP6 can be either double-, triple-, or
quad-buffered. EP4 and EP8 can only be double-buffered.
For high-speed endpoint configuration options, see
Figure 3-1.
Note:
3. if the descriptor loaded is set for remote wakeup enabled and the host does a set feature remote wakeup enabled, then the SX2 logic will perform RESUME
signalling after a WAKEUP interrupt.
Document #: 38-08013 Rev. *E
Page 4 of 42

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