您的位置：维库电子市场网 > Datasheet > CS5321-BL1

CS5321-BL1 Datasheet

  • CS5321-BL1

  • 24-Bit Variable Bandwidth A/D Converter Chipset

  • 756.22KB

  • CIRRUS

阅览下载 纠错 0

扫码查看芯片数据手册

上传产品规格书

PDF预览

CS5320/21/22
Note that a write will occur when CS = 0 and R/W
= 0 even if SCLK is not toggled. Failure to clock in
data with the appropriate number of SCLKs can
leave the configuration register in an indeterminate
condition.
The serial bit stream is received MSB first, LSB
last. The order of the input control data is PWDN
first, followed by ORCAL, USEOR, CSEL, Re-
served, DECC, DECB, and DECA. The configura-
tion data bits are defined in Table 2. The
configuration data controls device operation only
when in the software mode, i.e., the H/S pin is low
(H/S = 0). The Reserved configuration data bit
must always be written low.
(except when ORCAL = 1 and the CS5322 is RE-
SET as this toggles the ORCAL internally). After
ORCAL has been toggled, the SYNC signal must
be applied to the CS5322. The filter settles on the
input value in 56 output words. The output word
rate is determined by the state of the decimation
rate control pins, DECC, DECB, and DECA. On
the 57th output word, the CS5322 issues the OR-
CALD status flag, outputs the offset data sample,
and internally loads the offset register. During cal-
ibration, the offset register value is not used.
If USEOR is high (USEOR=1), subsequent sam-
ples will have the offset subtracted from the output.
The state of USEOR must remain high for the com-
plete duration of the convolution cycle. If USEOR
is low (USEOR=0), the output word is not correct-
ed, but the offset register retains its value for later
use. The results of the last calibration will be held
in the offset register until the end of a new calibra-
tion, or until the CS5322 is reset using the RESET
pin. USEOR does not alter the offset register value,
only its usage.
To restart a calibration, ORCAL and SYNC must
be taken low for at least one CLKIN cycle. OR-
CAL must then be taken high. The calibration will
restart on the next SYNC event. If the ORCAL pin
remains in a high state, only a single calibration
will start on the first SYNC signal.
2.16 Offset Calibration Operation
The offset calibration routine computes the offset
produced by the CS5320/21 modulator and stores
this value in the offset register. The USEOR pin or
bit determines if the offset register data is to be
used to correct output words.
After power is applied to the chip set the CS5322
must be RESET. To begin an offset calibration, the
CS5320/21 analog input must represent the offset
value. Then in software mode (H/S = 0) the OR-
CAL bit must be toggled from a low to a high. In
hardware mode the ORCAL pin must be toggled
low for at least one CLKIN cycle, then taken high
Input Bit #
1 (MSB)
2
3
4
5
6
7
8 (LSB)
Equivalent Hardware
Function
PWDN
ORCAL
USEOR
CSEL
Reserved
DECC
DECB
DECA
Description
Standby mode
Self-offset calibration
Use Offset Register
Channel Select
Factory use only
Filter BW selection
Filter BW selection
Filter BW selection
Table 2. Configuration Data Bits
DS454PP1
25

CS5321-BL1相关型号PDF文件下载

您可能感兴趣的PDF文件资料

热门IC型号推荐

©2025 维库电子市场网（www.dzsc.com）　备案号：浙B2-20050339-1 经营许可证：浙B2-20210386版权声明
买家服务热线：0571-85317607 | 买家服务部QQ： QQ:1609526468
卖家服务热线：0571-85317607 | 卖家服务部QQ： QQ:331652727

扫码下载APP，
一键连接广大的电子世界。

在线人工客服

买家服务：
卖家服务：
技术客服：

0571-85317607

网站技术支持

13606545031

客服在线时间周一至周五
9:00-17:30

关注官方微信号，
第一时间获取资讯。

建议反馈
返回顶部

建议反馈

联系人：

联系方式：

按住滑块，拖拽到最右边
>>
感谢您向阿库提出的宝贵意见，您的参与是维库提升服务的动力！意见一经采纳，将有感恩红包奉上哦！

PDF纠错X

投诉电话：0571-85317607 投诉QQ：

如选匿名将无法为您反馈投诉结果，建议实名投诉！