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HYB25D256800CL-6 Datasheet

  • HYB25D256800CL-6

  • 256 Mbit Double Data Rate SDRAM

  • 3260.54KB

  • 94页

  • INFINEON   INFINEON

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HYB25D256[16/40/80]0C[E/C/F/T](L)
256 Mbit Double-Data-Rate SDRAM
Functional Description
3
Functional Description
The 256 Mbit Double-Data-Rate SDRAM is a high-speed CMOS, dynamic random-access memory containing
268,435,456 bits. The 256 Mbit Double-Data-Rate SDRAM is internally configured as a quad-bank DRAM.
The 256 Mbit Double-Data-Rate SDRAM uses a double-data-rate architecture to achieve high-speed operation.
The double-data-rate architecture is essentially a
2n
prefetch architecture, with an interface designed to transfer
two data words per clock cycle at the I/O pins. A single read or write access for the
256 Mbit Double-Data-Rate SDRAM consists of a single
2n-bit
wide, one clock cycle data transfer at the internal
DRAM core and two corresponding n-bit wide, one-half clock cycle data transfers at the I/O pins.
Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and
continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration
of an Active command, which is then followed by a Read or Write command. The address bits registered
coincident with the Active command are used to select the bank and row to be accessed (BA0, BA1 select the
bank; A0-A12 select the row). The address bits registered coincident with the Read or Write command are used
to select the starting column location for the burst access.
Prior to normal operation, the DDR SDRAM must be initialized. The following sections provide detailed information
covering device initialization, register definition, command descriptions and device operation.
3.1
Initialization
DDR SDRAMs must be powered up and initialized in a predefined manner. Operational procedures other than
those specified may result in undefined operation. The following criteria must be met:
No power sequencing is specified during power up or power down given the following criteria:
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
A minimum resistance of 42
鈩?/div>
limits the input current from the
V
TT
supply into any pin and
V
REF
tracks
V
DDQ
/2
or the following relationship must be followed:
V
DDQ
is driven after or with
V
DD
such that
V
DDQ
<
V
DD
+ 0.3 V
V
TT
is driven after or with
V
DDQ
such that
V
TT
<
V
DDQ
+ 0.3 V
V
REF
is driven after or with
V
DDQ
such that
V
REF
<
V
DDQ
+ 0.3 V
V
DD
and
V
DDQ
are driven from a single power converter output
V
TT
meets the specification
The DQ and DQS outputs are in the High-Z state, where they remain until driven in normal operation (by a read
access). After all power supply and reference voltages are stable, and the clock is stable, the DDR SDRAM
requires a 200
碌s
delay prior to applying an executable command.
Once the 200
碌s
delay has been satisfied, a Deselect or NOP command should be applied, and CKE should be
brought HIGH. Following the NOP command, a Precharge ALL command should be applied. Next a Mode
Register Set command should be issued for the Extended Mode Register, to enable the DLL, then a Mode
Register Set command should be issued for the Mode Register, to reset the DLL, and to program the operating
parameters. 200 clock cycles are required between the DLL reset and any executable command. During the
200 cycles of clock for DLL locking, a Deselect or NOP command must be applied. After the 200 clock cycles, a
Precharge ALL command should be applied, placing the device in the 鈥渁ll banks idle鈥?state.
Once in the idle state, two AUTO REFRESH cycles must be performed. Additionally, a Mode Register Set
command for the Mode Register, with the reset DLL bit deactivated (i.e. to program operating parameters without
resetting the DLL) must be performed. Following these cycles, the DDR SDRAM is ready for normal operation.
Data Sheet
22
Rev. 1.6, 2004-12

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