5.13
t
CH
t
CK
t
CL
Figure 51
Data Sheet
VALID
NOP
NOP
NOP
NOP
PRE
NOP
NOP
ACT
CK
CK
t
IH
t
IS
CKE
t
IH
t
IS
Command
t
IH
Write: DM Operation
NOP
Write
t
IS
COL n
RA
A0-A9, A11, A12
t
IH
t
IS
ALL BANKS
RA
Figure 51
shows the timing diagram for DM Operation.
Write DM Operation (Burst Length = 4)
ONE BANK
t
IH
A10
DIS AP
89
BA x
BA x*
t
WR
t
DQSH
t
DQSS
t
DQSL
t
WPST
t
DSH
DIn
t
IS
BA
BA0, BA1
t
WPRES
t
RP
DQS
DQ
DM
HYB25D256[16/40/80]0C[E/C/F/T](L)
256 Mbit Double-Data-Rate SDRAM
Timing Diagrams
DI n = data in for column n.
3 subsequent elements of data in are applied in the programmed order following DI n (the second element of the 4 is masked).
DIS AP = Disable Auto Precharge.
*
= Don't care if A10 is High at this point.
PRE = Precharge; ACT = Active; RA = Row address; BA = Bank address.
NOP commands are shown for ease of illustration; other valid commands may be possible at these times.
t
DQSS
= min.
Rev. 1.6, 2004-12
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