HYB25D256[16/40/80]0C[E/C/F/T](L)
256 Mbit Double-Data-Rate SDRAM
Functional Description
3.5
3.5.1
Operations
Bank/Row Activation
Before any Read or Write commands can be issued to a bank within the DDR SDRAM, a row in that bank must
be 鈥渙pened鈥?(activated). This is accomplished via the Active command and addresses A0-A12, BA0 and BA1 (see
Figure 7),
which decode and select both the bank and the row to be activated. After opening a row (issuing an
Active command), a Read or Write command may be issued to that row, subject to the
t
RCD
specification. A
subsequent Active command to a different row in the same bank can only be issued after the previous active row
has been 鈥渃losed鈥?(precharged). The minimum time interval between successive Active commands to the same
bank is defined by
t
RC
. A subsequent Active command to another bank can be issued while the first bank is being
accessed, which results in a reduction of total row-access overhead. The minimum time interval between
successive Active commands to different banks is defined by
t
RRD
.
CK
CK
CKE
CS
RAS
CAS
WE
A0-A12
BA0, BA1
RA
BA
RA = row address.
BA = bank address.
Don鈥檛 Care
HIGH
Figure 7
Activating a Specific Row in a Specific Bank
CK
CK
Command
A0-A12
BA0, BA1
ACT
ROW
BA x
NOP
ACT
ROW
BA y
NOP
NOP
RD/WR
COL
BA y
NOP
NOP
t
RRD
t
RCD
Don鈥檛 Care
Figure 8
t
RCD
and
t
RRD
Definition
Data Sheet
30
Rev. 1.6, 2004-12