HYB25D256[16/40/80]0C[E/C/F/T](L)
256 Mbit Double-Data-Rate SDRAM
Functional Description
CAS Latency = 2
CK
CK
Command
Address
Read
BAa, COL n
BST
NOP
Write
BAa, COL b
NOP
NOP
CL=2
DQS
DQ
DM
DOa-n
t
DQSS
(min)
DI a-b
CAS Latency = 2.5
CK
CK
Command
Address
Read
BAa, COL n
BST
NOP
NOP
Write
BAa, COL b
NOP
CL=2.5
DQS
DQ
DM
DOa-n
t
DQSS
(min)
Dla-b
DO a-n = data out from bank a, column n
. a-b = data in to bank a, column b
DI
1 subsequent elements of data out appear in the programmed order following DO a-n.
Data In elements are applied following Dl a-b in the programmed order, according to burst length.
Shown with nominal t
AC
, t
DQSCK
, and t
DQSQ
.
Don鈥檛 Care
Figure 15
Read to Write: CAS Latencies (Burst Length = 4 or 8)
Data Sheet
39
Rev. 1.6, 2004-12