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HYB25D256800CL-6 Datasheet

  • HYB25D256800CL-6

  • 256 Mbit Double Data Rate SDRAM

  • 3260.54KB

  • 94页

  • INFINEON   INFINEON

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HYB25D256[16/40/80]0C[E/C/F/T](L)
256 Mbit Double-Data-Rate SDRAM
Electrical Characteristics
Table 22
Parameter
AC Timing - Absolute Specifications for PC2700
(cont鈥檇)
Symbol 鈥?
DDR266A
Min.
Write postamble
Write recovery time
Internal write to read command delay
Exit self-refresh to non-read command
Exit self-refresh to read command
2) Input slew rate
鈮?/div>
1 V/ns
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference
level for signals other than CK/CK, is
V
REF
. CK/CK slew rate are
鈮?/div>
1.0 V/ns.
4) Inputs are not recognized as valid until
V
REF
stabilizes.
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is
V
TT
.
6) For each of the terms, if not already an integer, round to the next highest integer.
t
CK
is equal to the actual system clock
cycle time.
7)
t
HZ
and
t
LZ
transitions occur in the same access time windows as valid data transitions. These parameters are not referred
to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
8) Fast slew rate
鈮?/div>
1.0 V/ns , slow slew rate
鈮?/div>
0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/
ns, measured between
V
IH(ac)
and
V
IL(ac)
.
9) These parameters guarantee device timing, but they are not necessarily tested on each device.
10) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
11) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge.
A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were
previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress,
DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on
t
DQSS
.
12) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but
system performance (bus turnaround) degrades accordingly.
13) In all circumstances,
t
XSNR
can be satisfied using
t
XSNR
=
t
RFC,min
+ 1
脳
t
CK
Unit
Max.
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Note/Test
Condition
1)
2)3)4)5)12)
2)3)4)5)
2)3)4)5)
2)3)4)5)13)
2)3)4)5)
t
WPST
t
WR
t
WTR
t
XSNR
t
XSRD
0.4
15
1
75
200
t
CK
ns
t
CK
ns
t
CK
1)
V
DDQ
= 2.5 V
卤
0.2 V,
V
DD
= +2.5 V
卤
0.2 V ; 0
掳C 鈮?/div>
T
A
鈮?/div>
70
掳C
Data Sheet
73
Rev. 1.6, 2004-12

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