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HYB25D256800CL-6 Datasheet

  • HYB25D256800CL-6

  • 256 Mbit Double Data Rate SDRAM

  • 3260.54KB

  • 94页

  • INFINEON   INFINEON

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HYB25D256[16/40/80]0C[E/C/F/T](L)
256 Mbit Double-Data-Rate SDRAM
Electrical Characteristics
Table 23
Parameter
I
DD
Conditions
Symbol
Operating Current:
one bank; active/ precharge;
t
RC
=
t
RCMIN
;
t
CK
=
t
CKMIN
;
DQ, DM, and DQS inputs changing once per clock cycle; address and control inputs changing once
every two clock cycles.
Operating Current:
one bank; active/read/precharge; Burst = 4;
Refer to the following page for detailed test conditions.
Precharge Power-Down Standby Current:
all banks idle; power-down mode; CKE
鈮?/div>
V
ILMAX
;
t
CK
=
I
DD0
I
DD1
I
DD2P
t
CKMIN
Precharge Floating Standby Current:
CS
鈮?/div>
V
IHMIN
, all banks idle;
I
DD2F
CKE
鈮?/div>
V
IHMIN
;
t
CK
=
t
CKMIN
, address and other control inputs changing once per clock cycle,
V
IN
=
V
REF
for DQ, DQS and DM.
Precharge Quiet Standby Current:
CS
鈮?/div>
V
IHMIN
, all banks idle; CKE
鈮?/div>
V
IHMIN
;
t
CK
=
t
CKMIN
, address and other control inputs stable
at
鈮?/div>
V
IHMIN
or
鈮?/div>
V
ILMAX
;
V
IN
=
V
REF
for DQ, DQS and DM.
Active Power-Down Standby Current:
one bank active; power-down mode;
CKE
鈮?/div>
V
ILMAX
;
t
CK
=
t
CKMIN
;
V
IN
=
V
REF
for DQ, DQS and DM.
I
DD2Q
I
DD3P
Active Standby Current:
one bank active; CS
鈮?/div>
V
IHMIN
; CKE
鈮?/div>
V
IHMIN
;
t
RC
=
t
RASMAX
;
t
CK
=
t
CKMIN
;
I
DD3N
DQ, DM and DQS inputs changing twice per clock cycle; address and control inputs changing once per
clock cycle.
Operating Current:
one bank active; Burst = 2; reads; continuous burst; address and control inputs
I
DD4R
changing once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR200
and DDR266A, CL = 3 for DDR333;
t
CK
=
t
CKMIN
;
I
OUT
= 0 mA
Operating Current:
one bank active; Burst = 2; writes; continuous burst; address and control inputs
I
DD4W
changing once per clock cycle; 50% of data outputs changing on every clock edge; CL = 2 for DDR200
and DDR266A, CL = 3 for DDR333;
t
CK
=
t
CKMIN
Auto-Refresh Current:
t
RC
=
t
RFCMIN
, burst refresh
Self-Refresh Current:
CKE
鈮?/div>
0.2 V; external clock on;
t
CK
=
t
CKMIN
Operating Current:
four bank; four bank interleaving with BL = 4; Refer to the following page for
detailed test conditions.
I
DD5
I
DD6
I
DD7
Data Sheet
74
Rev. 1.6, 2004-12

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