HYB25D256[16/40/80]0C[E/C/F/T](L)
256 Mbit Double-Data-Rate SDRAM
Timing Diagrams
5
5.1
Timing Diagrams
Write Command: Data Input Timing
The timing diagrams in this chapter give an overview of possible and recommended command sequences.
Figure 39
shows DQS versus DQ and DM Timing during write burst.
t
DQSL
t
DQSH
DQS
t
DH
t
DS
DQ
DI n
t
DH
t
DS
DM
DI n = Data In for column n.
3 subsequent elements of data in are applied in programmed order following DI n.
Don鈥檛 Care
Figure 39
Data Input (Write), Timing Burst Length = 4
Data Sheet
77
Rev. 1.6, 2004-12