5.6
Figure 44
Data Sheet
Clock must be stable before exiting Self Refresh Mode
t
CK
t
CH
t
CL
t
RP
*
200 cycles
Self Refresh Mode
t
IH
t
IS
t
IS
t
IH
t
XSRD,
t
XSRN
AR
NOP
VALID
t
IH
t
IS
VALID
CK
CK
t
IS
CKE
t
IS
Command
NOP
Figure 44
shows the timing diagram for Self Refresh Mode.
Refresh: Self Refresh Mode Command
82
Enter Self
Refresh Mode
Exit Self
Refresh Mode
ADDR
DQS
DQ
DM
HYB25D256[16/40/80]0C[E/C/F/T](L)
256 Mbit Double-Data-Rate SDRAM
*
= Device must be in the all banks idle state before entering Self Refresh Mode.
**
= t
XSNR
is required before any non-read command can be applied, and t
XSRD
(200 cycles of CK).
are required before a Read command can be applied.
Timing Diagrams
Rev. 1.6, 2004-12
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