5.12
Figure 50
t
CH
t
CK
t
CL
Data Sheet
VALID
t
RAS
ACT
NOP
Write
NOP
NOP
NOP
NOP
PRE
NOP
t
IH
t
IS
RA
Col n
t
IH
t
IS
RA
CK
CK
t
IH
t
IS
CKE
t
IH
t
IS
Command
NOP
A0-A9, A11, A12
Bank Write Access (Burst Length = 4)
ALL BANKS
ONE BANK
t
IH
t
IS
BA x
BA x
t
RCD
t
WPRES
t
DQSH
t
DQSS
t
DQSL
t
WPST
t
DSH
t
WR
BA x
Write: Bank Write Access Command
Figure 50
shows the timing diagram for Bank Write Access.
A10
DIS AP
88
DIn
t
WPRE
BA0, BA1
DQS
DQ
DM
HYB25D256[16/40/80]0C[E/C/F/T](L)
256 Mbit Double-Data-Rate SDRAM
t
DQSS
= min.
DI n = data in for column n.
3 subsequent elements of data in are applied in the programmed order following DI n.
DIS AP = Disable Auto Precharge.
*
= don't care if A10 is High at this point.
PRE = Precharge; ACT = Active; RA = Row address.
NOP commands are shown for ease of illustration; other valid commands may be possible at these times.
Timing Diagrams
Rev. 1.6, 2004-12
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