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ADC08D1500EVAL Datasheet

  • ADC08D1500EVAL

  • High Performance, Low Power, Dual 8-Bit, 1.5 GSPS A/D Conver...

  • 861.71KB

  • 33页

  • NSC

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ADC08D1500
Pin Descriptions and Equivalent Circuits
Pin Functions
Pin No.
83 / 78
84 / 77
85 / 76
86 / 75
89 / 72
90 / 71
91 / 70
92 / 69
93 / 68
94 / 67
95 / 66
96 / 65
100 / 61
101 / 60
102 / 59
103 / 58
104
105
106
107
111
112
113
114
115
116
117
118
122
123
124
125
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
57
56
55
54
50
49
48
47
46
45
44
43
39
38
37
36
Symbol
DI7鈭?/div>
DI7+
DI6鈭?/div>
DI6+
DI5鈭?/div>
DI5+
DI4鈭?/div>
DI4+
DI3鈭?/div>
DI3+
DI2鈭?/div>
DI2+
DI1鈭?/div>
DI1+
DI0鈭?/div>
DI0+
DId7鈭?/div>
DId7+
DId6鈭?/div>
DId6+
DId5鈭?/div>
DId5+
DId4鈭?/div>
DId4+
DId3鈭?/div>
DId3+
DId2鈭?/div>
DId2+
DId1鈭?/div>
DId1+
DId0鈭?/div>
DId0+
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
/
DQ7鈭?/div>
DQ7+
DQ6鈭?/div>
DQ6+
DQ5鈭?/div>
DQ5+
DQ4鈭?/div>
DQ4+
DQ3鈭?/div>
DQ3+
DQ2鈭?/div>
DQ2+
DQ1鈭?/div>
DQ1+
DQ0鈭?/div>
DQ0+
DQd7鈭?/div>
DQd7+
DQd6鈭?/div>
DQd6+
DQd5鈭?/div>
DQd5+
DQd4鈭?/div>
DQd4+
DQd3鈭?/div>
DQd3+
DQd2鈭?/div>
DQd2+
DQd1鈭?/div>
DQd1+
DQd0鈭?/div>
DQd0+
Equivalent Circuit
(Continued)
Description
I and Q channel LVDS Data Outputs that are not delayed in
the output demultiplexer. Compared with the DId and DQd
outputs, these outputs represent the later time samples.
These outputs should always be terminated with a 100鈩?/div>
differential resistor.
I and Q channel LVDS Data Outputs that are delayed by one
CLK cycle in the output demultiplexer. Compared with the
DI/DQ outputs, these outputs represent the earlier time
sample. These outputs should always be terminated with a
100鈩?differential resistor.
79
80
OR+
OR-
Out Of Range output. A differential high at these pins
indicates that the differential input is out of range (outside the
range
卤
325 mV or
卤
435 mV as defined by the FSR pin).
82
81
DCLK+
DCLK-
Differential Clock outputs used to latch the output data.
Delayed and non-delayed data outputs are supplied
synchronous to this signal. This signal is at 1/2 the input clock
rate in SDR mode and at 1/4 the input clock rate in the DDR
mode.
2, 5, 8,
13, 16,
17, 20,
25, 28,
33, 128
V
A
Analog power supply pins. Bypass these pins to ground.
5
www.national.com

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