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ADC08D1500EVAL Datasheet

  • ADC08D1500EVAL

  • High Performance, Low Power, Dual 8-Bit, 1.5 GSPS A/D Conver...

  • 861.71KB

  • 33页

  • NSC

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ADC08D1500
Absolute Maximum Ratings
(Notes 1, 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (V
A
, V
DR
)
Voltage on Any Input Pin
Ground Difference
|GND - DR GND|
Input Current at Any Pin (Note 3)
Package Input Current (Note 3)
Power Dissipation at T
A
鈮?/div>
85藲C
ESD Susceptibility (Note 4)
Human Body Model
Machine Model
Soldering Temperature, Infrared,
10 seconds, (Note 5), (Applies
to standard plated package only)
Storage Temperature
2.2V
鈭?.15V to (V
A
+0.15V)
0V to 100 mV
Operating Ratings
(Notes 1, 2)
Ambient Temperature Range
Supply Voltage (V
A
)
Driver Supply Voltage (V
DR
)
Analog Input Common Mode
Voltage
V
IN
+, V
IN
- Voltage Range
(Maintaining Common Mode)
Ground Difference
(|GND - DR GND|)
CLK Pins Voltage Range
Differential CLK Amplitude
鈭?0藲C
鈮?/div>
T
A
鈮?/div>
+85藲C
+1.8V to +2.0V
+1.8V to V
A
V
CMO
卤
50mV
200mV to V
A
0V
0V to V
A
0.4V
P-P
to 2.0V
P-P
卤
25 mA
卤
50 mA
2.0 W
2500V
250V
Package Thermal Resistance
Package
胃
JA
胃
JC (Top of
Package)
胃
J-PAD
(Thermal
Pad)
235藲C
鈭?5藲C to +150藲C
128-Lead
Exposed Pad
LQFP
26藲C / W
10藲C / W
2.8藲C / W
Converter Electrical Characteristics
NOTE: This product is currently in development and the parameters specified in this section are DESIGN TARGETS.
The specifications in this section cannot be guaranteed until device characterization has taken place.
The following
specifications apply after calibration for V
A
= V
DR
= +1.9V
DC
, OutV = 1.9V, V
IN
FSR (a.c. coupled) = differential 870mV
P-P
, C
L
= 10 pF, Differential, a.c. coupled Sinewave Input Clock, f
CLK
= 1.5 GHz at 0.5V
P-P
with 50% duty cycle, V
BG
= Floating, Non-
Extended Control Mode, SDR Mode, R
EXT
= 3300鈩?/div>
卤
0.1%, Analog Signal Source Impedance = 100鈩?Differential.
Boldface
limits apply for T
A
= T
MIN
to T
MAX
. All other limits T
A
= 25藲C, unless otherwise noted. (Notes 6, 7)
Symbol
Parameter
Conditions
Typical
(Note 8)
Limits
(Note 8)
Units
(Limits)
STATIC CONVERTER CHARACTERISTICS
INL
DNL
Integral Non-Linearity (Best fit)
Differential Non-Linearity
Resolution with No Missing
Codes
V
OFF
V
OFF
_ADJ
PFSE
NFSE
FS_ADJ
FPBW
B.E.R.
Offset Error
Input Offset Adjustment Range
Positive Full-Scale Error (Note
9)
Negative Full-Scale Error (Note
9)
Full-Scale Adjustment Range
Full Power Bandwidth
Bit Error Rate
Gain Flatness
d.c. to 500 MHz
d.c. to 1 GHz
f
IN
= 248 MHz, V
IN
= FSR 鈭?0.5 dB
ENOB
Effective Number of Bits
f
IN
= 498 MHz, V
IN
= FSR 鈭?0.5 dB
f
IN
= 748 MHz, V
IN
= FSR 鈭?0.5 dB
Extended Control Mode
Normal Mode (non DES)
Extended Control Mode
-0.45
DC Coupled, 1MHz Sine Wave
Overanged
DC Coupled, 1MHz Sine Wave
Overanged
卤
0.3
卤
0.15
卤
TBD
卤
TBD
8
鈭扵BD
TBD
LSB (max)
LSB (max)
Bits
LSB (min)
LSB (max)
mV
卤
45
鈭?.6
鈭?.31
卤
TBD
卤
TBD
卤
15
mV (max)
mV (max)
%FS
GHz
Error/Sample
dBFS
dBFS
卤
20
1.7
10
-18
NORMAL MODE (Non DES) DYNAMIC CONVERTER CHARACTERISTICS
卤
0.5
卤
1.0
7.4
7.4
7.25
TBD
TBD
TBD
Bits (min)
Bits (min)
Bits (min)
7
www.national.com

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