Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA
Signal
Name
GPIOD0
Pin
No.
55
Ball No.
Type
State
During
Reset
Input
Signal Description
P6
Input/
Output
Output
Port D GPIO
鈥?This GPIO pin can be individually programmed as an
input or output pin.
(CS2)
Tri-stated
Chip Select
鈥?CS2 may be programmed within the EMI module to act
as a chip select for specific areas of the external memory map.
Depending upon the state of the DRV bit in the EMI Bus Control
Register (BCR), CS2 is tri-stated when the external bus is inactive.
Most designs will want to change the DRV state to DRV = 1 instead of
using the default setting.
(CAN2_TX)
Open
Drain
Output
Output
FlexCAN2 Transmit Data
鈥?CAN output.
At reset, this pin is configured as GPIO. This configuration can be
changed by setting bit 0 in the GPIO_D_PER register. Then change bit
4 in the SIM_GPS register to select the desired peripheral function.
To deactivate the internal pull-up resistor, clear bit 0 in the
GPIOD_PUR register.
GPIOD1
56
L6
Schmitt
Input/
Output
Output
Input
Port D GPIO
鈥?This GPIO pin can be individually programmed as an
input or output pin.
(CS3)
Tri-stated
Chip Select
鈥?CS3 may be programmed within the EMI module to act
as a chip select for specific areas of the external memory map.
Depending upon the state of the DRV bit in the EMI Bus Control
Register (BCR), CS3 is tri-stated when the external bus is inactive.
Most designs will want to change the DRV state to DRV = 1 instead of
using the default setting.
(CAN2_RX)
Schmitt
Input
Input
FlexCAN2 Receive Data
鈥?This is the CAN input. This pin has an
internal pull-up resistor.
At reset, this pin is configured as GPIO. This configuration can be
changed by setting bit 1 in the GPIO_D_PER register. Then change bit
5 in the SIM_GPS register to select the desired peripheral function.
To deactivate the internal pull-up resistor, clear bit 1 in the
GPIOD_PUR register.
56F8367 Technical Data, Rev. 3.0
26
Freescale Semiconductor
Preliminary