Signal Pins
Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA
Signal
Name
RESET
Pin
No.
98
Ball No.
Type
State
During
Reset
Input
Signal Description
J14
Schmitt
Input
Reset
鈥?This input is a direct hardware reset on the processor. When
RESET is asserted low, the device is initialized and placed in the reset
state. A Schmitt trigger input is used for noise immunity. When the
RESET pin is deasserted, the initial chip operating mode is latched
from the EXTBOOT pin. The internal reset signal will be deasserted
synchronous with the internal clocks after a fixed number of internal
clocks.
To ensure complete hardware reset, RESET and TRST should be
asserted together. The only exception occurs in a debugging
environment when a hardware device reset is required and the
JTAG/EOnCE module must not be reset. In this case, assert RESET
but do not assert TRST.
Note:
The internal Power-On Reset will assert on initial power-up.
To deactivate the internal pull-up resistor, set the RESET bit in the
SIM_PUDR register. See
Part 6.5.6
for details.
RSTO
97
J13
Output
Output
Reset Output
鈥?This output reflects the internal reset state of the
chip.
External Boot
鈥?This input is tied to V
DD
to force the device to boot
from off-chip memory (assuming that the on-chip Flash memory is not
in a secure state). Otherwise, it is tied to ground. For details, see
Table 4-4.
Note:
When this pin is tied low, the customer boot software should
disable the internal pull-up resistor by setting the XBOOT bit of the
SIM_PUDR; see
Part 6.5.6.
EXTBOOT
124
B11
Schmitt
Input
Input
EMI_MODE
159
B2
Schmitt
Input
Input
External Memory Mode
鈥?This input is tied to V
DD
in order to enable
an extra four address lines, for a total of 20 address lines out of reset.
This function is also affected by EXTBOOT and the Flash security
mode. For details, see
Table 4-4.
If a 20-bit address bus is not desired, then this pin is tied to ground.
Note:
When this pin is tied low, the customer boot software should
disable the internal pull-up resistor by setting the EMI_MODE bit of the
SIM_PUDR; see
Part 6.5.6.
56F8367 Technical Data, Rev. 3.0
Freescale Semiconductor
Preliminary
37