XTAL
External
Clock
EXTAL
V
SS
Note: When using an external clocking source with
this configuration, the input 鈥淐LKMODE鈥?should be
high and the COHL bit in the OSCTL register
should be set to 1.
Figure 3-4 Connecting an External Clock Register
3.3 Registers
When referring to the register definitions for the OCCS in the
56F8300 Peripheral User Manual,
use the
register definitions
without
the internal Relaxation Oscillator, since the 56F8367/56F8167 do NOT
contain this oscillator.
Part 4 Memory Operating Modes (MEM)
4.1 Introduction
The 56F8367 and 56F8167 devices are 16-bit motor-control chips based on the 56800E core. These parts
use a Harvard-style architecture with two independent memory spaces for Data and Program. On-chip
RAM and Flash memory are used in both spaces.
This chapter provides memory maps for:
鈥?/div>
鈥?/div>
Program Address Space including the Interrupt Vector Table
Data Address Space including the EOnCE Memory and Peripheral Memory Maps
On-chip memory sizes for each device are summarized in
Table 4-1.
Flash memories鈥?restrictions are
identified in the 鈥淯se Restrictions鈥?column of
Table 4-1.
Note:
Data Flash and Program RAM are NOT available on the 56F8167 device.
Table 4-1 Chip Memory Configurations
On-Chip Memory
Program Flash
Data Flash
56F8367
512KB
32KB
56F8167
512KB
鈥?/div>
Use Restrictions
Erase/Program via Flash interface unit and word writes to
CDBW
Erase/Program via Flash interface unit and word writes to
CDBW. Data Flash can be read via one of CDBR or XDB2, but
not both simultaneously
None
None
Erase/Program via Flash Interface unit and word to CDWB
Program RAM
Data RAM
Program Boot Flash
4KB
32KB
32KB
鈥?/div>
32KB
32KB
56F8367 Technical Data, Rev. 3.0
40
Freescale Semiconductor
Preliminary
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