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MC56F8367MPYE Datasheet

  • MC56F8367MPYE

  • 16-bit Digital Signal Controllers

  • 2743.16KB

  • 180页

  • FREESCALE

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Table 4-4 Program Memory Map at Reset
Mode 0 (MA = 0)
Begin/End
Address
Internal Boot
Internal Boot
16-Bit External Address Bus
P:$1F FFFF
P:$10 0000
P:$0F FFFF
P:$05 0000
P:$04 FFFF
P:$04 F800
P:$04 F7FF
P:$04 4000
P:$04 3FFF
P:$04 0000
Mode 1
1
(MA = 1)
External Boot
EMI_MODE = 0
2
,
3
16-Bit External Address Bus
EMI_MODE = 1
4
20-Bit External Address Bus
External Program Memory
6
External Program Memory
5
External Program Memory
5
On-Chip Program RAM
4KB
Reserved
92KB
Boot Flash
32KB
COP Reset Address = 04 0002
Boot Location = 04 0000
Internal Program Flash
8
256KB
Boot Flash
32KB
(Not Used for Boot in this Mode)
Internal Program Flash
256KB
Internal Program Flash
128KB
External Program Memory
COP Reset Address = 00 0002
Boot Location = 00 0000
External Program Memory
COP Reset Address = 04 0002
7
Boot Location = 04 0000
7
P:$03 FFFF
P:$02 0000
P:$01 FFFF
P:$01 0000
P:$00 FFFF
P:$00 0000
Internal Program Flash
8
256KB
1. If Flash Security Mode is enabled, EXTBOOT Mode 1 cannot be used. See
Security Features,
Part 7.
2. This mode provides maximum compatibility with 56F80x parts while operating externally.
3. 鈥淓MI_MODE = 0鈥?when EMI_MODE pin is tied to ground at boot up.
4. 鈥淓MI_MODE = 1鈥?when EMI_MODE pin is tied to V
DD
at boot up.
5. Not accessible in reset configuration, since the address is above P:$00 FFFF. The higher bit address/GPIO (and/or chip
selects) pins must be reconfigured before this external memory is accessible.
6. Not accessible in reset configuration, since the address is above P:$0F FFFF. The higher bit address/GPIO (and/or chip
selects) pins must be reconfigured before this external memory is accessible.
7. Booting from this external address allows prototyping of the internal Boot Flash.
8. Two independent program flash blocks allow one to be programmed/erased while executing from another. Each block must
have its own mass erase.
4.3 Interrupt Vector Table
Table 4-5
provides the reset and interrupt priority structure, including on-chip peripherals. The table is
organized with higher-priority vectors at the top and lower-priority interrupts lower in the table. The
priority of an interrupt can be assigned to different levels, as indicated, allowing some control over
interrupt priorities. All level 3 interrupts will be serviced before level 2, and so on. For a selected priority
level, the lowest vector number has the highest priority.
56F8367 Technical Data, Rev. 3.0
42
Freescale Semiconductor
Preliminary

MC56F8367MPYE 产品属性

  • 40

  • 集成电路 (IC)

  • 嵌入式 - 微控制器，

  • 56F8xxx

  • 56800E

  • 16-位

  • 60MHz

  • CAN，EBI/EMI，SCI，SPI

  • POR，PWM，温度传感器，WDT

  • 76

  • 544KB（272K x 16）

  • 闪存

  • -

  • 18K x 16

  • 2.25 V ~ 3.6 V

  • A/D 16x12b

  • 外部

  • -40°C ~ 125°C

  • 160-LQFP

  • 托盘

  • MC56F8367EVME-ND - EVAL BOARD FOR MC56F83X

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