Interrupt Vector Table
The location of the vector table is determined by the Vector Base Address (VBA) register. Please see
Part
5.6.11
for the reset value of the VBA.
In some configurations, the reset address and COP reset address will correspond to vector 0 and 1 of the
interrupt vector table. In these instances, the first two locations in the vector table must contain branch or
JMP instructions. All other entries must contain JSR instructions.
Note:
PWMA, FlexCAN, Quadrature Decoder 1, and Quad Timers B and D are NOT available on the
56F8167 device.
Table 4-5 Interrupt Vector Table Contents
1
Peripheral
Vector
Number
Priority
Level
Vector Base
Address +
Interrupt Function
Reserved for Reset Overlay
2
Reserved for COP Reset Overlay
2
core
core
core
core
core
core
2
3
4
5
6
7
3
3
3
3
1-3
1-3
P:$04
P:$06
P:$08
P:$0A
P:$0C
P:$0E
Illegal Instruction
SW Interrupt 3
HW Stack Overflow
Misaligned Long Word Access
OnCE Step Counter
OnCE Breakpoint Unit 0
Reserved
core
core
core
9
10
11
1-3
1-3
1-3
P:$12
P:$14
P:$16
OnCE Trace Buffer
OnCE Transmit Register Empty
OnCE Receive Register Full
Reserved
core
core
core
core
core
14
15
16
17
18
2
1
0
0-2
0-2
P:$1C
P:$1E
P:$20
P:$22
P:$24
SW Interrupt 2
SW Interrupt 1
SW Interrupt 0
IRQA
IRQB
Reserved
LVI
PLL
FM
FM
FM
20
21
22
23
24
0-2
0-2
0-2
0-2
0-2
P:$28
P:$2A
P:$2C
P:$2E
P:$30
Low-Voltage Detector (power sense)
PLL
FM Access Error Interrupt
FM Command Complete
FM Command, data and address Buffers Empty
Reserved
56F8367 Technical Data, Rev. 3.0
Freescale Semiconductor
Preliminary
43