您的位置：维库电子市场网 > Datasheet > 24c02
24c02数据手册封面

24c02 Datasheet

  • 24c02

  • 24c02

  • 145.59KB

  • 16页

  • STMicroelectronics

纠错 0

扫码查看芯片数据手册

上传产品规格书

PDF预览

ST24/25C02, ST24C02R, ST24/25W02
SIGNAL DESCRIPTIONS
(cont鈥檇)
The devices with this Write Control feature no
longer support the Multibyte Write mode of opera-
tion, however all other write modes are fully sup-
ported.
Refer to the AN404 Application Note for more de-
tailed information about Write Control feature.
DEVICE OPERATION
I
2
C Bus Background
The ST24/25x02 support the I
2
C protocol. This
protocol defines any device that sends data onto
the bus as a transmitter and any device that reads
the data as a receiver. The device that controls the
data transfer is known as the master and the other
as the slave. The master will always initiate a data
transfer and will provide the serial clock for syn-
chronisation. The ST24/25x02 are always slave
devices in all communications.
Start Condition.
START is identified by a high to
low transition of the SDA line while the clock SCL
is stable in the high state. A START condition must
precede any command for data transfer. Except
during a programming cycle, the ST24/25x02 con-
tinuously monitor the SDA and SCL signals for a
START condition and will not respond unless one
is given.
Stop Condition.
STOP is identified by a low to high
transition of the SDA line while the clock SCL is
stable in the high state. A STOP condition termi-
nates communication between the ST24/25x02
and the bus master. A STOP condition at the end
of a Read command, after and only after a No
Acknowledge, forces the standby state. A STOP
condition at the end of a Write command triggers
the internal EEPROM write cycle.
Acknowledge Bit (ACK).
An acknowledge signal
is used to indicate a successfull data transfer. The
bus transmitter, either master or slave, will release
the SDA bus after sending 8 bits of data. During the
9th clock pulse period the receiver pulls the SDA
bus low to acknowledge the receipt of the 8 bits of
data.
Data Input.
During data input the ST24/25x02
sample the SDA bus signal on the rising edge of
the clock SCL. Note that for correct device opera-
tion the SDA signal must be stable during the clock
low to high transition and the data must change
ONLY when the SCL line is low.
Memory Addressing.
To start communication be-
tween the bus master and the slave ST24/25x02,
the master must initiate a START condition. Follow-
ing this, the master sends onto the SDA bus line 8
bits (MSB first) corresponding to the device select
code (7 bits) and a READ or WRITE bit.
Figure 3. Maximum R
L
Value versus Bus Capacitance (C
BUS
) for an I
2
C Bus
20
VCC
16
RL
RL
RL max (k鈩?
12
MASTER
8
SDA
SCL
CBUS
CBUS
4
VCC = 5V
0
100
200
CBUS (pF)
300
400
AI01100
4/16

24c02 PDF文件相关型号

ST24/25C02,ST24/25W02,ST24C02B1TR,ST24C02B5TR,ST24C02B6TR,ST24C02M3TR,ST24C02R,ST24C02RB1TR,ST24C02RB3TR,ST24C02RB5TR,ST24C02RB6TR,ST24C02RM1TR,ST24C02RM3TR,ST24C02RM5TR,ST24W02B1TR,ST24W02B5TR,ST24W02B6TR,ST24W02M3TR,ST25C02B1TR,ST25C02B5TR,ST25C02B6TR,ST25C02M3TR,ST25W02B1TR,ST25W02B3TR,ST25W02B5TR,ST25W02B6TR,ST25W02M1TR,ST25W02M3TR,ST25W02M5TR

24c02相关型号PDF文件下载

您可能感兴趣的PDF文件资料

热门IC型号推荐

©2024 维库电子市场网（www.dzsc.com）　备案号：浙B2-20050339-1 经营许可证：浙B2-20210386版权声明
买家服务热线：0571-85317607 | 买家服务部QQ： QQ:1609526468
卖家服务热线：0571-85317607 | 卖家服务部QQ： QQ:331652727

扫码下载APP，
一键连接广大的电子世界。

在线人工客服

买家服务：
卖家服务：

0571-85317607

客服在线时间周一至周五
9:00-17:30

关注官方微信号，
第一时间获取资讯。

建议反馈
返回顶部

建议反馈

联系人：

联系方式：

按住滑块，拖拽到最右边
>>
感谢您向阿库提出的宝贵意见，您的参与是维库提升服务的动力！意见一经采纳，将有感恩红包奉上哦！

PDF纠错X

投诉电话：0571-85317607 投诉QQ：

如选匿名将无法为您反馈投诉结果，建议实名投诉！