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ST24/25C02, ST24C02R, ST24/25W02

Table 3. Device Select Code

Device Code

Bit

Device Select

Note:

The MSB b7 is sent first.

Chip Enable

b4

0

b3

E2

b2

E1

b1

E0

RW

b0

RW

b7

1

b6

0

b5

1

Table 4. Operating Modes

(1)

Mode

Current Address Read

Random Address Read

Sequential Read

Byte Write

Multibyte Write

(2)

Page Write

RW bit

鈥?鈥?/div>

X

V

IH

V

IL

1 to 256

1

4

8

MODE

X

Bytes

1

Initial Sequence

START, Device Select, RW = 鈥?鈥?/div>

START, Device Select, RW = 鈥?鈥? Address,

reSTART, Device Select, RW = 鈥?鈥?/div>

Similar to Current or Random Mode

START, Device Select, RW = 鈥?鈥?/div>

Notes:

1. X = V

IH

or V

IL

2. Multibyte Write not available in ST24/25W02 versions.

When writing data to the memory it responds to the

8 bits received by asserting an acknowledge bit

during the 9th bit time. When data is read by the

bus master, it acknowledges the receipt of the data

bytes in the same way. Data transfers are termi-

nated with a STOP condition.

Power On Reset: V

CC

lock out write protect.

In

order to prevent data corruption and inadvertent

write operations during power up, a Power On

Reset (POR) circuit is implemented. Until the V

CC

voltage has reached the POR threshold value, the

internal reset is active, all operations are disabled

and the device will not respond to any command.

In the same way, when V

CC

drops down from the

operating voltage to below the POR threshold

value, all operations are disabled and the device

will not respond to any command. A stable V

CC

must be applied before applying any logic signal.

SIGNAL DESCRIPTIONS

Serial Clock (SCL).

The SCL input pin is used to

synchronize all data in and out of the memory. A

resistor can be connected from the SCL line to V

CC

to act as a pull up (see Figure 3).

Serial Data (SDA).

The SDA pin is bi-directional

and is used to transfer data in or out of the memory.

It is an open drain output that may be wire-OR鈥檈d

with other open drain or open collector signals on

the bus. A resistor must be connected from the SDA

bus line to V

CC

to act as pull up (see Figure 3).

Chip Enable (E2 - E0).

These chip enable inputs

are used to set the 3 least significant bits (b3, b2,

b1) of the 7 bit device select code. These inputs

may be driven dynamically or tied to V

CC

or V

SS

to

establish the device select code.

Mode (MODE).

The MODE input is available on pin

7 (see also WC feature) and may be driven dynami-

cally. It must be at V

IL

or V

IH

for the Byte Write

mode, V

IH

for Multibyte Write mode or V

IL

for Page

Write mode. When unconnected, the MODE input

is internally read as a V

IH

(Multibyte Write mode).

Write Control (WC).

An hardware Write Control

feature (WC) is offered only for ST24W02 and

ST25W02 versions on pin 7. This feature is usefull

to protect the contents of the memory from any

erroneous erase/write cycle. The Write Control sig-

nal is used to enable (WC = V

IH

) or disable (WC =

V

IL

) the internal write protection. When uncon-

nected, the WC input is internally read as V

IL

and

the memory area is not write protected.

3/16

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24c02 PDF文件相关型号

ST24/25C02,ST24/25W02,ST24C02B1TR,ST24C02B5TR,ST24C02B6TR,ST24C02M3TR,ST24C02R,ST24C02RB1TR,ST24C02RB3TR,ST24C02RB5TR,ST24C02RB6TR,ST24C02RM1TR,ST24C02RM3TR,ST24C02RM5TR,ST24W02B1TR,ST24W02B5TR,ST24W02B6TR,ST24W02M3TR,ST25C02B1TR,ST25C02B5TR,ST25C02B6TR,ST25C02M3TR,ST25W02B1TR,ST25W02B3TR,ST25W02B5TR,ST25W02B6TR,ST25W02M1TR,ST25W02M3TR,ST25W02M5TR

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