74LVC169 Datasheet_PDF文件下载_芯片资料查询

Philips Semiconductors

Product specification

Presettable synchronous 4-bit up/down

binary counter

74LVC169

STATE DIAGRAM

0

1

2

3

4

TYPICAL TIMING SEQUENCE

MR

PE

15

5

D0

D1

14

6

D2

D3

13

7

CP

12

11

10

9

8

CEP

CET

COUNT DOWN

COUNT UP

Q0

SF00788

Q1

Q2

Q3

FUNCTION TABLE

OPERATING

MODES

Parallel load

(Dn鈫扱n)

Count Up

(increment)

Count Down

(decrement)

Hold

(do nothing)

INPUTS

CP

鈫?/div>

U/D

X

h

l

X

CEP

X

l

h

X

CET

X

l

X

PE

l

X

h

D

n

l

X

OUTPUTS

Q

n

L

H

Count

Up

Count

Down

q

n

q

n

TC

*

H

TC

12

13

14

15

0

1

2

INHIBIT

RESET PRESET

COUNT

SY00069

Typical timing sequence: reset outputs to zero; preset to binary

twelve; count to thirteen, fourteen, fifteen, zero, one, and two;

inhibit

H = High voltage level steady state

h = High voltage level one setup time prior to the Low-to-High

clock transition

L = Low voltage level steady state

l = Low voltage level one setup time prior to the Low-to-High

clock transition

q = Lower case letters indicate the state of the referenced output

prior to the Low-to-High clock transition

X = Don鈥檛 care

鈫?/div>

= Low-to-High clock transition

* = The TC is Low when CET is Low and the counter is at

Terminal Count.

Terminal Count Up is (HHHH) and Terminal Count Down is

(LLLL).

1998 May 20

4

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