93C66A/B
3.8
WRITE
3.9
Write All (WRAL)
The WRITE instruction is followed by 8 bits (93C66A)
or 16 bits (93C66B) of data which are written into the
speci铿乪d address. After the last data bit is clocked into
the DI pin the self-timed auto-erase and programming
cycle begins.
The DO pin indicates the READY/BUSY status of the
device, if CS is brought high after a minimum of 250 ns
low (T
CSL
) and before the entire write cycle is complete.
DO at logical 鈥?鈥?indicates that programming is still in
progress. DO at logical 鈥?鈥?indicates that the register at
the speci铿乪d address has been written with the data
speci铿乪d and the device is ready for another instruc-
tion.
The WRAL instruction will write the entire memory
array with the data speci铿乪d in the command. The
WRAL cycle is completely self-timed and commences
at the rising clock edge of the last data bit. Clocking of
the CLK pin is not necessary after the device has
entered the WRAL cycle. The WRAL command does
include an automatic ERAL cycle for the device. There-
fore, the WRAL instruction does not require an ERAL
instruction but the chip must be in the EWEN status.
The DO pin indicates the READY/BUSY status of the
device if CS is brought high after a minimum of 250 ns
low (T
CSL
).
FIGURE 3-7:
CS
WRITE TIMING
T
CSL
CLK
DI
1
0
1
An
鈥⑩€⑩€?/div>
A0
Dx
鈥⑩€⑩€?/div>
D0
T
SV
T
CZ
READY
DO
HIGH-Z
BUSY
HIGH-Z
Twc
FIGURE 3-8:
CS
WRAL TIMING
T
CSL
CLK
DI
1
0
0
0
1
X
鈥⑩€⑩€?/div>
X
Dx
鈥⑩€⑩€?/div>
D0
T
SV
T
CZ
DO
HIGH-Z
BUSY
READY
HIGH-Z
T
WL
漏
1998 Microchip Technology Inc.
Preliminary
DS21207B-page 7
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