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AD7663 Datasheet

  • AD7663

  • 16-Bit 1 MSPS SAR Unipolar ADC with Ref

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  • 26页

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PRELIMINARY TECHNICAL DATA
AD7667
decision made during the first half of the conversion
phase. For this reason, it is recommended that when an
external clock is being provided, it is a discontinuous
clock that is toggling only when BUSY is low or, more
importantly, that it does not transition during the latter
half of BUSY high.
External Discontinuous Clock Data Read After Conver-
sion
valid on both rising and falling edge of the clock. The 16
bits have to be read before the current conversion is com-
plete. If that is not done, RDERROR is pulsed high and
can be used to interrupt the host interface to prevent
incomplete data reading. There is no 鈥渄aisy chain鈥?/div>
feature in this mode and RDC/SDIN input should al-
ways be tied either high or low.
To reduce performance degradation due to digital activity, a
fast discontinuous clock of, at least 25 MHz, when impulse mode is
used, 32 MHz when normal mode is used or 40 MHz when
warp mode is used, is recommended to ensure that all the bits
are read during the first half of the conversion phase. It is
also possible to begin to read the data after conversion and
continue to read the last bits even after a new conversion has
been initiated. That allows the use of a slower clock speed like
18 MHz in impulse mode, 21 MHz in normal mode and 26
MHz in warp mode.
MICROPROCESSOR INTERFACING
Though the maximum throughput cannot be achieved using
this mode, it is the most recommended of the serial slave
modes. Figure 18 shows the detailed timing diagrams of this
method. After a conversion is complete, indicated by BUSY
returning low, the result of this conversion can be read while
both
CS
and
RD
are low. The data is shifted out, MSB first,
with 16 clock pulses and is valid on both rising and falling
edge of the clock.
Among the advantages of this method, the conversion perfor-
mance is not degraded because there are no voltage transients
on the digital interface during the conversion process.
Another advantage is to be able to read the data at any speed
up to 40 MHz which accommodates both slow digital host
interface and the fastest serial reading.
Finally, in this mode only, the AD7667 provides a 鈥渄aisy-
chain鈥?feature using the RDC/SDIN input pin for cascading
multiple converters together. This feature is useful for reducing
component count and wiring connections when desired as, for
instance, in isolated multiconverter applications.
An example of the concatenation of two devices is shown in
Figure 19. Simultaneous sampling is possible by using a com-
mon
CNVST
signal. It should be noted that the RDC/SDIN
input is latched on the edge of SCLK opposite to the one used to
shift out the data on SDOUT. Hence, the MSB of the 鈥渦pstream鈥?/div>
converter just follows the LSB of the 鈥渄ownstream鈥?converter
on the next SCLK cycle.
BUSY
OUT
BUSY
BUSY
The AD7667 is ideally suited for traditional dc measure-
ment applications supporting a microprocessor, and ac signal
processing applications interfacing to a digital signal processor.
The AD7667 is designed to interface either with a parallel 16-
bit-wide interface or with a general-purpose serial port or I/O
ports on a microcontroller. A variety of external buffers can be
used with the AD7667 to prevent digital noise from coupling
into the ADC. The following sections illustrate the use of the
AD7667 with an SPI-equipped microcontroller, the ADSP-
21065L and ADSP-218x signal processors.
SPI Interface (MC68HC11)
Figure 21 shows an interface diagram between the AD7667
and an SPI-equipped microcontroller like the MC68HC11. To
accommodate the slower speed of the microcontroller, the
AD7667 acts as a slave device and data must be read after
conversion. This mode allows also the 鈥渄aisy chain鈥?feature.
The convert command could be initiated in response to
an internal timer interrupt. The reading of output data,
one byte at a time, if necessary, could be initiated in
response to the end-of-conversion signal (BUSY going
low) using to an interrupt line of the microcontroller. The
Serial Peripheral Interface (SPI) on the MC68HC11 is
configured for master mode (MSTR = 1), Clock Polar-
ity Bit (CPOL) = 0, Clock Phase Bit (CPHA) = 1 and
SPI Interrupt Enable (SPIE = 1) by writing to the SPI Con-
trol Register (SPCR). The IRQ is configured for
edge-sensitive-only operation (IRQE = 1 in OPTION
register).
AD7667
#2
(UPSTREAM)
RDC/SDIN
SDOUT
CNVST
CS
SCLK
AD7667
#1
(DOWNSTREAM)
RDC/SDIN
SDOUT
CNVST
CS
SCLK
DATA
OUT
SCLK IN
CS IN
CNVST IN
Figure 19. Two AD7667s in a 鈥淒aisy-Chain鈥?Configuration
External Clock Data Read During Conversion
Figure 20 shows the detailed timing diagrams of this
method. During a conversion, while both
CS
and
RD
are
both low, the result of the previous conversion can be read.
The data is shifted out, MSB first, with 16 clock pulses and is
鈥?0鈥?/div>
REV. PrA

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