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AD7663 Datasheet

  • AD7663

  • 16-Bit 1 MSPS SAR Unipolar ADC with Ref

  • 1337.63KB

  • 26页

  • AD

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PRELIMINARY TECHNICAL DATA
AD7667
Parameter
Operating Current
4
AVDD
5
DVDD
5
OVDD
5
Power Dissipation
5
without REF
Power Dissipation
5
with REF
TEMPERATURE RANGE
8
Specified Performance
Conditions
1 MSPS Throughput
Min
Typ
TBD
TBD
TBD
112
15
TBD
122
10.015
TBD
鈥?0
+85
Max
Unit
mA
mA
碌A
mW
碌W
碌W
mW
mW
碌W
1 MSPS Throughput
100 SPS Throughput
6
In Power-Down Mode
7
1 MSPS Throughput
100 SPS Throughput
6
In Power-Down Mode
7
T
MIN
to T
MAX
掳C
NOTES
1
LSB means Least Significant Bit. With the 0 V to 2.5 V input range, one LSB is 38.15 碌V.
2
See Definition of Specifications section. These specifications do not include the error contribution from the external reference.
3
All specifications in dB are referred to a full-scale input FS. Tested with an input signal at 0.5 dB below full-scale unless otherwise specified.
4
In warp mode.
5
Tested in parallel reading mode using external reference.
6
In impulse mode with external REF.
7
With all digital inputs forced to DVDD or DGND respect
ively.
8
Contact factory for extended temperature range.
9
The max should be the minimum of 5.25V and DVDD+0.3 V.
Specifications subject to change without notice.
TIMING SPECIFICATIONS
(鈥?0 C to +85 C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.)
Symbol
REFER TO FIGURES 11 AND 12
Convert Pulsewidth
Time Between Conversions
(Warp Mode/Normal Mode/Impulse Mode)
CNVST
LOW to BUSY HIGH Delay
BUSY HIGH All Modes Except in
Master Serial Read After Convert Mode
(Warp Mode/Normal Mode/Impulse Mode)
Aperture Delay
End of Conversion to BUSY LOW Delay
Conversion Time
(Warp Mode/Normal Mode/Impulse Mode)
Acquisition Time
RESET Pulsewidth
REFER TO FIGURES 13, 14, AND 15 (Parallel Interface Modes)
CNVST
LOW to DATA Valid Delay
(Warp Mode/Normal Mode/Impulse Mode)
DATA Valid to BUSY LOW Delay
Bus Access Request to DATA Valid
Bus Relinquish Time
REFER TO FIGURES 16 AND 17 (Master Serial Interface Modes)
2
CS
LOW to SYNC Valid Delay
CS
LOW to Internal SCLK Valid Delay
2
CS
LOW to SDOUT Delay
CNVST
LOW to SYNC Delay
(Warp Mode/Normal Mode/Impulse Mode)
SYNC Asserted to SCLK First Edge Delay
Internal SCLK Period
3
Internal SCLK HIGH
3
Internal SCLK LOW
3
SDOUT Valid Setup Time
3
SDOUT Valid Hold Time
3
SCLK Last Edge to SYNC Delay
3
CS
HIGH to SYNC HI-Z
CS
HIGH to Internal SCLK HI-Z
CS
HIGH to SDOUT HI-Z
BUSY HIGH in Master Serial Read after Convert
3
(Warp Mode/Normal Mode/Impulse Mode)
CNVST
LOW to SYNC Asserted Delay
(Warp Mode/Normal Mode/Impulse Mode)
SYNC Deasserted to BUSY LOW Delay
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
t
11
t
12
t
13
t
14
t
15
t
16
t
17
t
18
t
19
t
20
t
21
t
22
t
23
t
24
t
25
t
26
t
27
t
28
t
29
t
30
3
25
12
7
4
2
3
45
5
40
15
10
10
10
25/275/525
2
10
0.75/1/1.25
250
10
0.75/1/1.25
Min
5
1/1.25/1.5
Typ
Max
Unit
ns
碌s
ns
碌s
Note 1
30
0.75/1/1.25
ns
ns
碌s
ns
ns
碌s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
碌s
碌s
ns
40
10
10
10
See Table I
0.75/1/1.25
25
REV. PrA
鈥?鈥?/div>

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