10. Pulse widths less than minimum values are not allowed.
11. Values guaranteed by design, not currently tested.
12.
PAFasynch
, t
PAEasynch
, after program register write will not be valid until 5 ns + t
PAF(E)
.
13. t
SKEW1
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH during the current clock cycle. If the time between the
rising edge of RCLK and the rising edge of WCLK is less than t
SKEW1
, then FF may not change state until the next WCLK edge.
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