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TDA8357J Datasheet

  • TDA8357J

  • Full bridge vertical deflection output

  • 109.49KB

  • Philips

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Philips Semiconductors
Preliminary speci铿乧ation
Full bridge vertical de铿俥ction output circuit
in LVDMOS
SYMBOL
Flyback switch
I
o(peak)
V
loss(FB)
maximum (peak) output current
voltage loss at 铿倅back
t
鈮?/div>
1.5 ms
note 11
I
o
= 0.7 A
I
o
= 1.0 A
Guard circuit
V
O(grd)
guard output voltage
I
O(grd)
= 100
碌A
maximum leakage current
I
L(max)
= 10
碌A
V
O(grd)
= 0 V; not active
V
O(grd)
= 4.5 V; active
Notes
5
鈭?/div>
鈭?/div>
1
6
鈭?/div>
鈭?/div>
鈭?/div>
鈭?/div>
鈭?/div>
7.5
8
鈭?/div>
鈭?/div>
PARAMETER
CONDITIONS
MIN.
TYP.
TDA8357J
MAX.
卤1.2
8.5
9
UNIT
A
V
V
7
18
10
2.5
V
V
碌A
mA
V
O(grd)(max)
allowable guard voltage
I
O(grd)
output current
1. To limit V
OUTA
to 68 V, V
FB
must be 66 V due to the voltage drop of the internal flyback diode between pins OUTA
and V
FB
at the first part of the flyback.
2. Allowable input range: V
I(bias)
+ V
i(dif)
< 1600 mV and V
I(bias)
鈭?/div>
V
i(dif)
> 100 mV for each input.
3. This value specifies the sum of the voltage losses of the internal current paths between pins V
P
and OUTA, and
between pins OUTB and GND. Specified for T
j
= 125
掳C.
The temperature coefficient for V
loss(1)
is a positive value.
4. This value specifies the sum of the voltage losses of the internal current paths between pins V
P
and OUTB, and
between pins OUTA and GND. Specified for T
j
= 125
掳C.
The temperature coefficient for V
loss(2)
is a positive value.
5. The linearity error is measured for a linear input signal without S-correction and is based on the 鈥榦n screen鈥?/div>
measurement principle. This method is defined as follows. The output signal is divided in 22 successive equal time
blocks k. The 1st and 22nd blocks are ignored, while the voltage amplitudes are measured across R
M
, starting at
k = 2 and ending at k = 21, where V
k
and V
k+1
are the measured voltages of two successive blocks. V
min
, V
max
and
V
avg
are the minimum, maximum and average voltages respectively. The linearity errors are defined as:
V
k
鈥?/div>
V
k
+
1
a) LE
=
------------------------- (adjacent blocks)
-
V
avg
V
max
鈥?/div>
V
min
b) LE
=
------------------------------ (non adjacent blocks)
-
V
avg
6. The linearity errors are specified for a minimum input voltage of 300 mV (p-p). Lower input voltages lead to voltage
dependent S-distortion in the input stage.
7.
V
OUTA
鈥?/div>
V
OUTB
G
v
(
ol
)
=
-------------------------------------------
-
V
FEEDB
鈥?/div>
V
OUTB
8. Pin FEEDB not connected.
9.
V
FEEDB
鈥?/div>
V
OUTB
G
v
=
-------------------------------------------
-
V
INA
鈥?/div>
V
INB
10. V
P(ripple)
= 500 mV (RMS value); 50 Hz < f
P(ripple)
< 1 kHz; measured across R
M
.
11. This value specifies the internal voltage loss of the current path between pins V
FB
and OUTA.
1999 Nov 10
7

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