This page is a summary of the projects and students under Paul Gray and Robert Meyer at the University of California at Berkeley.

The focus of our group is designing analog circuits for high integratiON. We have emphasized analog CMOS design techniques because an increasing portion of today's integrated circuit functionality is being performed in the digital domain by VLSI circuits implemented in a CMOS technology. Achieving high integration requires both all the analog signal processing and the associated analog-to-digital interface to be built with the same technology as the digital circuits.

A large effort is also being expended on the design of high-frequency, BiCMOS and Bipolar integrated circuits. Currently work is being done on power amplifiers, mixers, and low-noise pre-amplifiers.

What's New?

This page contains links to recently created documents, as well as links to updated pages within this site. Re-visit this page to find new documents as they are made.

Dec 2001

• R. S. Narayanaswami, "RF CMOS Class C Power Amplifiers for Wireless Communications"(PDF), PhD Thesis, University of California, Berkeley, Dec 2001.
  

Feb 2001

• " A 1.75-GHz Highly-Integrated Narrow-Band CMOS Transmitter with Harmonic- Rejection Mixers," J.Weldon, J.Rudell, L.Lin, R.Narayanswami, M.Otsuka, S.Dedieu, L.Tee, K. Tsai, C.Lee and P.Gray Presentation for the 2001 International Solid State Circuits Conference Feb. 6th, 2001

Dec 2000

• N. Sneed, " A 2-GHz CMOS LC-Tuned VCO using Switched-Capacitors to Compensate for Bond Wire Inductance Variation," (PDF) MS Thesis, University of California, Berkeley, Dec 2000.
  
• G. Desjardins, "Adapative Digital Signal Processing Algorithms for Image-Rejection Mixer Self-Calibration," (PDF) MS Thesis, University of California, Berkeley, Dec 2000.

Nov 2000

• L. Lin, " Design Techniques of High Performance Integrated Frequency Synthesizer for Multi-standard Wireless Communication Applications," (PDF) Ph.D. Thesis, University of California, Berkeley, Nov 2000.

Feb 2000

• G. Chien, P.R. Gray, " A 900-MHz Local Oscillator using a DLL-based Frequency Multiplier Technique for PCS Applications," (PDF) Digest of Technical Papers, International Solid-State Circuits Conference, San Francisco, CA. Feb. 8, 2000
• L. Lin, L. Tee, P.R. Gray" A 1.4GHz Differential Low-Noise CMOS Frequency Synthesizer using a Wideband PLL Architecture," (PDF) Digest of Technical Papers, International Solid-State Circuits Conference, San Francisco, CA. Feb. 8, 2000

Jan 2000

• G. Chien, "Low-Noise Local Oscillator Design Techniques using a DLL-based Frequency Multiplier for Wireless Applications," (PDF) Ph.D. Thesis, University of California, Berkeley, Jan 2000. Available as ERL Memo M00/4.

May 1999

• A. Abo, "Design for Reliability of Low-voltage, Switched-capacitor Circuits," (PDF 635kB) PhD Thesis, University of California, Berkeley, May, 1999. Available as ERL Memo M99/25.
  
• A. Abo, P. R. Gray, "A 1.5-V, 10-bit, 14.3-MS/s CMOS Pipeline Analog-to-Digital Converter," (PDF) IEEE J. Solid-State Circuits, vol. 34, no. 5, May 1999.
  
• A. Abo, "Preliminary Design of a 1.5V, 10-bit, 14.3-MS/s CMOS Pipeline ADC," (PDF)
  

July 1998

• J.C. Rudell, J.J. Ou, R. S. Narayanaswami, G. Chien, J.A. Weldon, L. Lin, K.C. Tsai, L. Tee, K. Khoo, D. Au, T. Robinson, D. Gerna, M. Otsuka, and P. R. Gray, " Recent Developments in High Integration Multi-Standard CMOS Transceivers for Personal Communication Systems ,"(PDF) Invited paper at the 1998 International Symposium on Low Power Electronics, Monterey, California.

  ---

June 1998

• A. Abo, P. R. Gray, "A 1.5V, 10-bit, 14MS/s CMOS Pipeline Analog-to-Digital Converter," (PDF-paper) 1998 Symposium on VLSI Circuits, Honolulu, June 1998.
  
• A. Abo, Paul R. Gray, "A 1.5V, 10-bit, 14MS/s CMOS Pipeline Analog-to-Digital Converter," (PDF/GIF/MIF/PS-slides) 1998 Symposium on VLSI Circuits, June, 1998.
  
• C. J. Barrett, "Low-Power Decimation Filter Design for Multi-Standard Transceiver Applications," (PDF) UC Berkeley MS Thesis, December 1997.
  
• R. S. Narayanaswami, "The Design of a 1.9GHz 250mW CMOS Power Amplifier For DECT" (HTML) (PS, PDF), UC Berkeley MS Thesis, May 1998.
  

April 1998

• Monolithic CMOS RF Transceiver Page -- This Page has been updated to reflect the full Transceiver project that is ongoing here.

February 1997

• RF Short Course, ISSCC, San Francisco, Feb 1997.

• Slides for " A 1.9GHz Wide-Band IF Double Conversion CMOS Integrated Receiver for Cordless Telephone Applications," J.Rudell, JJ. Ou, T.Cho, G.Chien, F.Brianti, J.Weldon, and P.Gray. Presentation for the 1997 International Solid-State Circuits Conference (GIF/MIF/PS) Feb. 8th, 1997

• Digest paper for " A 1.9GHz Wide-Band IF Double Conversion CMOS Integrated Receiver for Cordless Telephone Applications," J.Rudell, JJ. Ou, T.Cho, G.Chien, F.Brianti, J.Weldon, and P.Gray. 1997 International Solid-State Circuits Conference (GIF/MIF/PS) Feb. 8th, 1997

September 1996

• T. Cho, G. Chien, F. Brianti and P. R. Gray, "A Power-Optimized CMOS Baseband Channel Filter and ADC for Cordless Applications" (GIF/MIF/PS) VLSI Circuit Conference Digest 96, June 1996.
  
• T.Cho, J.Rudell, P. R. Gray, et al, " A Multi-Standard Monolithic CMOS RF Transceiver (Overview / Status)," (HTML/MIF/PS) June 16, 1996.
  
• J. Rudell, G. Chien, J. Weldon, C. Barrett, L. Lin, M. Tsai, L. Tee, M. Sabatini, and P. R. Gray, " Second Generation Multi-Standard Monolithic CMOS RF Transceiver," (HTML/MIF/PS) June 16, 1996.
  
• L. Lin, "Design Techniques for Parallel Pipelined ADC", (PS), UC Berkeley MS Thesis, May 1996.

RF Integrated Circuit Design

With the recent explosive growth of the Telecommunications industry, research in this field has taken on critical importance. The major issues being investigated are higher levels of integration, lower power designs, and lower cost solutions. These issues are being addressed in a number of ways, and with several different technologies. Current research is in the area of design of Mixers, Power Amplifiers (PAs), Low Noise Amplifiers (LNAs), Frequency Synthesizers, Intermediate Frequency circuits (IF), and Baseband circuits.
To meet the ever-increasing consumer demand for portable low-cost, low-power transceivers used in PCS, cordless and cellular telephone applications we are investigating highly integrated transceiver solutions. To address the integration issue we are exploring receiver and transmit path architectures that facilate integration of all transceiver blocks on a single silicon substrate. In addition, we seek to develop a radio system that is somewhat generic allowing a single radio to be utilized by multiple RF standards. An example application might be a portable phone with a single transceiver allowing the user to us both a cordless and cellular network for communication. On the circuit level, we are developing solutions that allow the integration of the higher frequency blocks like the LNA and mixer in a standard low-cost CMOS process also leaving the possibility of integrating all the analog blocks with the digital backend.
The multi-standard transceiver project was initiated with a single chip CMOS receiver designed to meet the specifications of the Digital Enhanced Cordless Telecommunications (DECT) standard. This device was fabricated and tested throughout 1996. Currently, we are designing a single-chip transceiver for the GSM standard which is schedule to tapeout in early 1998.

Monolithic CMOS RF Transceiver

Simplified transceiver block diagram: click on a block to see who's working on it.

The goal of this project is to integrate a complete monolithic radio transceiver in CMOS. The project presents many new challenges in CMOS RF design. We are targeting both the DCS 1800 (a variant of the popular GSM standard) and DECT (Digital European Cordless Telephone) standard as a demonstration of the multi-standard capability of this approach Blocks currently under design include: receiver system design, LNA,image-reject mixer (adaptive image-reject mixer, mixer design), frequency synthesizer (LC tank based PLL, delay-locked loop (DLL), pider), continuous-time anti-aliasing filter, A/D converter, up-conversion mixers, and power amplifiers(Class C Power Amplifier, Class E Power Amplifier).

Technical documents

• Technical papers
• Presentation slides
• Theses

People

Monolithic RF MixersMixers are very important building blocks in any RF systems. Downconversion mixers link together the low-noise amplifier, local oscillator and IF stage of which the performances are interrelated. Their highly nonlinear behavior makes analysis and optimization difficult. This behavior can cause noise and spurious signals to move across frequencies.
A large amount of effort has been expended by group researchers in the design and optimization of monolithic RF mixers. Current work is being carried out in Bipolar, CMOS and BiCMOS technologies. Systematic ways that will provide close-to-optimal active mixer designs are being investigated. New low power techniques such as class AB mixers have been demonstrated. Work on self-calibrated image-reject mixers may provide an interesting way to improve system integration.

Technical documents

• Technical papers
• Presentation slides
• Theses

People

Monolithic RF Mixers

Mixers are very important building blocks in any RF systems. Downconversion mixers link together the low-noise amplifier, local oscillator and IF stage of which the performances are interrelated. Their highly nonlinear behavior makes analysis and optimization difficult. This behavior can cause noise and spurious signals to move across frequencies.
A large amount of effort has been expended by group researchers in the design and optimization of monolithic RF mixers. Current work is being carried out in Bipolar, CMOS and BiCMOS technologies. Systematic ways that will provide close-to-optimal active mixer designs are being investigated. New low power techniques such as class AB mixers have been demonstrated. Work on self-calibrated image-reject mixers may provide an interesting way to improve system integration.

Technical documents

• Technical papers
• Presentation slides
• Theses

People

Integrated Power Amplifier Design

Power Amplifiers (PAs) play a critical part in determining the power efficiency of a RF system because of their high output power levels, which can reach 3W for some cellular systems. As a result the design of highly efficient PAs is of great importance. At the same time, many types of modulation require linear PAs. Meeting all the necessary requirements makes PA design very challenging.
In the past GaAs, and discrete solutions have dominated the area of PA design. The higher cost and lower level of integration provided by these two solutions makes them less desirable in future systems. Because of this several members of the group are currently investigating the issue of PA design, with a major emphasis on integration with the rest of the transceiver. Both linear and non-linear PA design is being investigated using Bipolar, BiCMOS, and CMOS technologies.

Technical documents

• Technical papers
• Presentation slides
• Theses

People

Graduates

RF Device Modeling

Proper modeling of RF Devices is necessary, when designing circuits that operate at frequencies greater than 900MHz. Because of this we have spent time investigating accurate ways to model RF devices, and their interaction through the substrate. Current research focuses primarily on spiral inductor modeling, but past research included substrate modeling, and high frequency device modeling.

Technical documents

• Technical papers
• Presentation slides
• Theses

People

Data Communications Circuit Design

As the performance demands of modern systems increase in the next few years, a corresponding increase in the bandwidth of the networks tying these systems together must also occur. Our research is focused on Fiber based solutions because of their extremely high bandwidth. In particular we have taken an interest in SONET. Currently we are looking at the design of a Low-Noise Transimpedance amplifier, which is the most critical part of the transceiver.

Technical documents

• Technical papers
• Presentation slides
• Theses

People

High Speed, Low Power CMOS ADC's

Much of our research has focused on the pipeline ADC, which lends itself to high-speed, low-power solutions suited to CMOS implementation. Potential applications include video imaging, wireless LAN, personal communication systems, and disk drive read channels. In such applications, it is highly desirable for both power and cost that the ADC be integrable with digital VLSI functions on the same chip. This integration requires low sensitivity to supply noise, compatibility with single-poly technology, and ability to operate on low supply voltages.

Technical documents

• Technical papers
• Presentation slides
• Theses

People

Analog CAD

We have a few analog CAD projects in collaboration with other research groups. These projects focus on circuit synthesis given constraints and specifications.

A related research group is the Analog CAD Research Group.

Technical documents

• Technical papers
• Presentation slides
• Theses

People

Presentation slides, Papers, and Theses

Technical papers and slides from presentations are online in various formats PDF, Postscript (PS), GIF, HTML, and MIF (Framemaker Interchange Format). Not all formats may be present at this time.

• Technical papers
• Presentation slides
• Theses
• 1997 ERL Research Summary Abstracts

To send for hardcopies of UCB EE theses see also:

• Electronics Research Laboratory Technical Reports
• UC Berkeley CS Technical Reports

People

Faculty

Graduate Students

Recent Graduates

Visiting Fellows

Staff